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Intel widens lead in high-k/metal gate race

Posted: 12 Dec 2008 ?? ?Print Version ?Bookmark and Share

Keywords:Intel high-k metal gate? 32nm? EUV? microprocessor?

Intel Corp. is expected to extend its lead over Advanced Micro Devices Inc., IBM and other microprocessor vendors in the high-k/metal-gate race at next week's International Electron Devices Meeting (IEDM).

In a paper, Intel will describe a new 45nm derivative for SoC designs based on high-k/metal-gate technology. In addition, the chip giant will provide more details about its previously-announced, 32nm process, based on a second-generation, high-k/metal-gate architecture. And, Intel will talk about a quantum well field effect transistor technology.

It is also working on its 22nm technology, which is in R&D. While it did not elaborate on this technology, the company acknowledged that it may end up processing its 22nm designs using 193nm immersion scanners, meaning extreme ultraviolet (EUV) lithography is late to the partyagain.

Regarding two other key technologieshigh-k and metal-gatesa big question remains: Can Intel's competitors catch up? To date, Intel's main rival, AMD, has announced its 45nm processors, but the devices reportedly do not use a high-k/metal-gate scheme.

AMD's technology partner, IBM Corp., does not expect to have its high-k/metal-gate solution until the 32nm node, reportedly causing some angst in the market. IBM's "fab club" is using a gate-first approach to high-k and metal gates, while Intel is deploying a rival replacement-gate technology.

High-k lead
For some time, Intel has already shipped 45nm processors based on the technology, giving it an edge in the market. High-k and metal gates are key building blocks for scaling and reducing the leakage within the critical gate stack, enabling the next-generation transistor.

High-k uses a material called hafnium to replace the transistor's silicon dioxide gate dielectric, which is running out of gas in today's designs. Also on the transistor, a metal material replaces the polysilicon gate electrode of NMOS and PMOS structures.

Despite an endless parade of claims made by vendors, high-k/metal-gate technology is much harder to develop than previously thought. IBM's "fab club" is reportedly wrestling with the technology, while the foundries will not deploy the scheme until the 32- or 28nm nodes.

With the exception of Intel, "nobody else is shipping high-k yet," said Mark Bohr, Intel senior fellow and director of process architecture and integration. "We have more than a one generation lead in technology," Bohr told EE Times.

Moving to 32nm
At IEDM, Intel will present several papers on the subject, including at 32nm. As far back as late-2007, the chip giant rolled out its initial 32nm test chip. The device has a 0.171?? cell size containing more than 1.9 billion transistors.

Then, in October of 2008, the company tipped its 32nm process. As reported, the process incorporates copper interconnects, a second-generation high-k/metal-gate technology and a fourth-generation strained-silicon scheme.

Intel is expected to deploy its first immersion lithography scanners at 32nm. The 193nm machines will be sole sourced from Nikon Corp.

The transistors feature dual band-edge workfunction metal gates and high-k gate dielectrics with an equivalent oxide thickness (EOT) of 9nm or 9?. In comparison, the company's 45nm high-k designs have an EOT of 10nm. The 32nm version enables Intel to reduce transistor variability," Bohr said.

At 32nm, Intel's transistor gate pitch is 112.5nm. Intel's 32nm logic technology provides about 70 percent linear feature size scaling and 50 percent area scaling, as compared to the company's 45nm process. In addition, the process enables the highest drive currents reported to date for 32nm technology.

Intel is on track for 32nm production readiness in Q4 09. Meanwhile, the company is also working on its 22nm process. The technology will make use of 193nm immersion scanners with either double-patterning or computational lithography techniques, he said. For 22nm, EUV "probably won't be ready," he said.

- Mark LaPedus
EE Times





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