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PCIe 2.0 IP supports 65nm node

Posted: 13 Jan 2009 ?? ?Print Version ?Bookmark and Share

Keywords:PCIe IP 2.0? property intellectual? process 65nm?

Renesas Technology America Inc. has achieved certification of a new logical- and physical-layer intellectual property (IP) conforming to PCIe Base Specification rev 2.0 (PCIe 2.0).

This IP allows data transfers at up to 5Gbit/s and supports the 65nm semiconductor process node. Microcontrollers, microprocessors and SoC devices incorporating this IP can make easy connections to other devices that support the PCIe 2.0 standard.

Renesas plans to release the first products incorporating the new IP in 2009. The new devices are targeted for graphics, storage and other applications that must rapidly transfer large volumes of data.

High speed data transfer
The company plans to eventually extend to process nodes even finer than 65nm and to provide enhanced functionality for key applications such as an increased number of lanes. To facilitate development work by customers, system environment evaluations will be promoted, including the PCI-SIG Compliance Program.

PCIe is a high-speed serial interface employing differential signaling. The maximum transfer speed of the latest Rev. 2.0 standard is 5Gbit/s, double that of the 2.5Gbit/s of the earlier Rev. 1.1 standard.

The upgraded capability translates into high-speed data transfer at an effective rate of 500MBps per lane. For this reason, more sophisticated and difficult design technology is required to realize circuits that can handle Rev. 2.0.

Microprocessor or SoC products incorporating this certified IP will enable developers to create high-speed systems capable of transferring large volumes of data very rapidly.

The new IP implements an up-configuration function that dynamically switches the transfer rate during operation. When high-speed data transfer is required, multiple lanes can be used, with each operating at the maximum transfer speed of 5Gbit/s. When the transfer volume is lower, priority is given to reducing power consumption. Only one lane operates at a transfer speed of 2.5Gbit/s, which is half the maximum rate.

The new Renesas IP achieves power consumption up to 50 percent less per Gbps than the company's earlier IP, which supports Rev. 1.1. The combination of the existing power-management function and the new up-configuration function contribute to substantial decreases in overall system power consumption.

When the new IP is incorporated into products such as MCUs, microprocessors or SoCs, customers will be able to select function options suitable for their target systems.

The main function options will include device attributes (root port/endpoint selection), maximum payload size, number of virtual channels, number of functions, on-chip buffer size and number of lanes. By combining these options appropriately, customers will be able to realize an LSI product that is ideal for the system they are developing.

- Bernard Cole
Embedded.com





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