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IBM 'fab club' tips 28nm high-k process

Posted: 20 Apr 2009 ?? ?Print Version ?Bookmark and Share

Keywords:28nm high-k process? technology metal gate? IBM fab club? foundry industry?

Right recipe
IBM's technology alliance claims to have the right solution for 32- and 28nm. Pushing the newer technology, Patton implied that it makes more sense to migrate from 65nm (or above) to 32-/28nm, thereby skipping the 45-/40nm nodes.

The 45-/40nm processes are a "weak node" and being ramp up "much later than anticipated," he said. Weak economic conditions, coupled with "leakage issues," have hampered the overall adoption of the 45-/40nm nodes, he said.

Instead of shifting to that node, chipmakers would be better off from IC designs at the 32-/28nm nodesequipped with high-k, he said. The low-power, 28nm technology platform is ideal for a broad range of power-sensitive mobile and consumer electronics applications.

The first 28nm process is based on a bulk, low-power technology. IBM did not disclose when it would offer a high-performance version or other derivatives of the process.

The 28nm, high-k and metal gate implementation from IBM allows for one of the industry's smallest SRAM cells at 0.120?m?, with low minimum voltage operation, leakage and stability. Preliminary results working with early access partners indicate that the 28nm technology platform can provide a 40 percent performance improvement and a more than 20 percent reduction in powerall in a chip that is half the sizecompared with 45nm technology, according to IBM.

Unlike the traditional polysilicon and silicon dioxide schemes for the gate stack, high-k and metal gate breaks down the barrier of scaling, allowing power and performance advantage without the need for complex processes, thereby lowering total development cost.

There are two basic approaches to the next-generation gate stack in logic designs. IBM's "fab club" is using a gate-first approach to the high-k/metal-gate scheme, while Intel is deploying a rival replacement-gate technology. In a gate-first approach, the gate stack is formed before the source and drain, as in a conventional CMOS process. Replacement-gate technologies are a gate-last approach, where the gate stack is formed after source and drain.

Both approaches use a hafnium-based material, but the entire semiconductor community is mum about their respective high-k recipes. High-k has been difficult to develop and chip makers do not want to divulge any secrets.

For high-k, it is widely believed Intel is using atomic layer deposition (ALD), based on reactors from ASM International BV. ASMI is also Intel's tool supplier for low-k. Nikon Corp. is reportedly Intel's sole lithography vendor for the 32nm node. For 45nm, Intel has been using scanners from Nikon and ASML Holding NV.

IBM is reportedly using ALD based on tools from Tokyo Electron Ltd. For the most part, IBM and its partners are using 193nm lithography gear from ASML.

- Mark LaPedus
EE Times


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