Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > T&M
?
?
T&M??

Memory model generator trims verification time

Posted: 09 Jun 2009 ?? ?Print Version ?Bookmark and Share

Keywords:verification? memory model generator? SDRAM?

India-based eInfochips has launched a memory model generator based on the DDR2 SDRAM SystemVerilog Verification Methodology Manual approach.

The tool will generate behavioral models for leading memory vendors including Elpida, Hynix, Micron and Samsung. The tool is designed to reduce the time needed for verification while maximizing memory coverage, the company claims.

The memory model generator allows the configuration of the parameters for DDR2 SDRAM memory, including memory size, data width, clock and data rate, cycle time and CAS latency. The memory generator also preserves a library of part numbers for each supported memory vendor.

In "typical mode," users can choose vendors and part numbers to generate the memory model. In "custom mode," designers can create behavioral models by configuring the memory parameters using a configuration selection algorithm.

- K.C. Krishnadas
TechOnline India





Article Comments - Memory model generator trims verific...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top