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DAC panel revisits DFM debate

Posted: 31 Jul 2009 ?? ?Print Version ?Bookmark and Share

Keywords:DFEM? design for manufacturing? IC design?

Design for manufacturing (DFM) reared its ugly head again at the Design Automation Conference (DAC). The consensus is that DFM has its place in the chip design world, but basically it's a crapshoot.

"It's a band aid with diminishing returns," said Kimon Michaels, VP design and co-founder at PDF Solutions. "At the leading edge of chip design, new materials and reduced line width margins require that manufacturing be considered as part of the design cycle."

But the benefit of DFM for mainstream design is questionable, according to Prasad Subramaniam, VP, design technology at eSilicon. "Cutting-edge designs need DFM to improve yield of acceptable manufactured chips. But in mainstream design, sound design practices can yield designs less sensitive to the need of DFM."

Michaels and Subramaniam were joined by execs from Cambridge Silicon Radio (CSR), Taiwan Semiconductor Manufacturing Co., and Virage Logic in a panel discussion at the DAC: "DFMBand-Aid or Competitive Weapon?"

Joe Sawicki, VP and general manager for the design-to-silicon division at Mentor Graphics, moderated and asked panelists to answer one question: "Can DFM give designers a competitive 'lever' by telling them how far they can push a design without creating a manufacturing disaster?"

It turns out DFM has a definite role to play, but not many are able to pinpoint real gains from using DFM tools or as a methodology in design.

"DFM is many things to many people," said Mark Redford, VP advanced technology development at CSR. "DFM tools need to be part of the design flow and foundries need to provide statistically valid data that covers the layout styles of their product portfolio."

Kuo Wu, deputy director of TSMC's product and design services marketing division, was more conciliatory about the DFM conundrum: "We are all in this together. Foundries, EDA tool providers and designers have standardized on a very effective GDS-centric community that enables to use one exchange format to hand over to the foundry." Wu said the current generation of process nodes have lithography line variations out of norm and cannot be represented by a Spice model.

"The restricted design rules you hear so much about is not a new concept adopted at 65nm node designs. Rules by definition are restrictive, only today the number of rules is increasing with each new process generation and you much tighter restrictions at the smaller geometries. What we can't get away from is that the physics only lets us do so much," said Wu.

"We need to go to restricted layouts, not only to restricted design rules," said PDF's Michaels.

"What we need is a process by which we can enable designers to measure specific return-on-investment that DFM tools might provide," said Yervant Zorian, VP and chief scientist at Virage Logic. "It's a disservice to the designer to have him or her choose among many DFM tools offered and not know what ROI the chosen tool will bring in terms of yields."

"We should also discriminate hard to manufacture parts of chips like analog portions from the relative easier digital parts of an SoC in order to tackle the process variability challenge," concluded TSMC's Wu.

- Nicolas Mokhoff
EE Times





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