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Debug chip designs with FPGA-powered emulators

Posted: 25 Aug 2009 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA emulators? chip design debug?

Creating a hardware emulation system is no easy task. At a minimum, each generation of emulation system has to accommodate a growing number of logic gates, memory and DSP blocks to allow ASIC and ASSP SoC designers to debug their extremely complex devices before sending them off to the foundry for production. Emulation systems must also be easy to program, reliable and affordable.

Today's SoCs are exceedingly complex pieces of silicon. They contain one or more processors that will execute software. The software code they run is every bit as important a part of the final system as the silicon itself. The software and the silicon have to act as a seamless solution; if there's a problem, it might be the software, or it might be the silicon.

Designers can only do so much software testing on a development host. No reasonable host development system can reflect the true parallelism of the target SoC. You can really only test out such issues as synchronization, data integrity and resource contention in situ, and that's far too late to identify problems. Simulation isn't a viable solution; it's simply too slow to allow the execution of any realistic code.

As a result, engineers have been using emulation systems for well over two decades to verify the most advanced ICs the semiconductor industry can build. Most of these earlier-generation emulation systems were powered by custom ICs that the emulator vendors designed themselves. They would then pass the cost of the custom IC development on to their customers, making the power of emulation more cost-prohibitive for companies struggling with tighter IC development budgets.

In 2001, EVE broke with tradition by basing its emulation system on Xilinx FPGAs. The goal was to provide the lowest hardware-assisted verification cost of ownership in the industry, as achieved through a combination of high execution speed, high capacity (which today means up to a billion gates), quick design revision, flexible and powerful debugging capabilities, lowest cost per gate and most cycles per dollar. In addition, we wanted to make the system easy to use for ASIC designers who might not be familiar with FPGA design.

The result was the ZeBu (for "zero bug") emulation system. We've now developed six generations of emulators, the most recent of which is ZeBu Server.

View the PDF document for more information.





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