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Improve yield with layout-aware DFT

Posted: 08 Oct 2009 ?? ?Print Version ?Bookmark and Share

Keywords:DFT? design for test? layout yield?

Design for test (DFT) has come a long way in testing the validity of the designed hardware. The growing gate counts with complex SoC architectures and nanometer scaling has exploded test data volume, multiple test methods and also increased test application time. The exploding test data volumes do not ensure the corresponding test quality improvement.

The better and smarter approachalong with the traditional approach for test generation tools to improve the test qualitywill be to use the physical layout information of the design. The top-up pattern generated with relevant physical parameters information will not only help in improving the test quality, but also in better failure analysis. This article discusses the approach to figure out those areas from the layout that has higher probability of physical malfunctioning. The DFT tools can then generate top-up test patterns for these areas. Such layout-aware DFT will be useful for better focus on testing, failure analysis and thus improving yield.

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