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IF reference kit eases base station design

Posted: 22 Oct 2009 ?? ?Print Version ?Bookmark and Share

Keywords:IF reference design? base station? radio receiver? WiMAX?

SP16160CH1RB reference design

From National Semiconductor Corp. comes an IF sampling receiver reference design kit for multi-carrier, multi-standard wireless base stations addressing GSM/Edge, W-CDMA, LTE and WiMAX standards. The kit provides radio designers with all the necessary technical material to accelerate the design and development of high-performance radio receivers: reference design board, software, schematic, BOM and Gerber files.

The SP16160CH1RB reference design board facilitates evaluation of the IF receive signal path performance under a variety of input conditions. When combined with a low-noise, high-linearity RF front-end and sufficient IF filtering, the reference design enables high sensitivity receivers that exceed the stringent multi-carrier GSM requirements in both normal and blocking conditions. Improved receiver sensitivity translates to enhanced base station capacity and coverage, allowing service providers to reach more customers and deliver a higher quality of service.

The SP16160CH1RB delivers an IF chain receiver sensitivity of -105dBm, with a 9dB carrier-to-noise ratio in a 200kHz channel, at 192MHz input IF. With the digitally-controlled variable gain amplifier (DVGA) set at a maximum gain of 22dB, the sensitivity is limited primarily by the noise contribution of the DVGA. In the presence of a strong blocker, with the DVGA gain set at 12dB and blocker level kept at 1.6dBm input to the ADC, the SP16160CH1RB board delivers sensitivity of -86dBm. In this blocking condition, the receiver sensitivity is determined by the ADC's high spurious-free dynamic range (SFDR).

The SP16160CH1RB operates from a single 5V supply and includes the dual-channel ADC16DV160 16-bit, 160MSps pipeline ADC, dual-channel LMH6517 DVGA, and LMK04031B clock jitter cleaner. The overall performance of the reference design is enabled by the high dynamic performance of the ADC, the low-noise and high-linearity of the DVGA and ultralow rms jitter of the clock jitter cleaner. The ADC16DV160 delivers a SNR of 76.3dBFS and SFDR of 91.2dBFS at 192MHz input IF, while the LMH6517 provides a noise figure of 6dB and OIP3 of 45dBm, and the LMK04031B clock jitter cleaner offers near 150fsec of rms clock jitter.

To simplify evaluation of the SP16160CH1RB, National offers the WaveVision 5.1 data capture board and WaveVision 5 software, which enables data capture and analysis, as well as complete programmable configuration of the ADC16DV160 and LMH6517 via a common SPI bus. Included with the SP16160CH1RB board, is a PIC loader board for configuring the LMK04031B.

Available now, the SP16160CH1RB subsystem reference design kit is priced at $995 each.





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