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Converter clocking tech extends to high speed data clocks (Part II)

Posted: 26 Oct 2009 ?? ?Print Version ?Bookmark and Share

Keywords:converter clock? data clocks jitter? clocking technology?

Part I of this article reviewed clocking requirements for data converter systems. The clocks for these systems are often referred to as "converter clocks." In high-speed data networks, the transmit and receive functions are implemented without data conversion. These systems are designed to reliably transfer pre-digitized data and are better classified as "data clocks."

A network line card clock system is discussed as an example of a data clocking application. Line card clocking is a prevalent network clock application, and there are a range of implementations depending on the required transport protocol.

The line card clock system receives an input reference from either a main timing card via a backplane or from a clock recovered from a synchronous signal received from the network. This input reference is jitter filtered, frequency translated and then distributed to the framer, FEC and Serdes blocks. In the transmit section, the Framer maps the data received over the backplane into frames appropriate for the protocol in use (SONET, Gigabit Ethernet etc.). The framer can also add FEC coding. The framed and coded data is clocked as parallel bytes into the serializer block and is converted to a high rate serial data stream. This data stream is either transmitted along an electrical transmission line or input into an optical module, which converts the electrical signal into an optical signal to be transmitted over fiber.

The receive process is essentially the reverse process except that a clock and data recovery (CDR) circuit is used at the interface to the transmission line or optical module to extract the received clock reference from the incoming data signal. As mentioned, this clock is sometimes used as a reference for the transmit section. There are variations on this line card topology and timing scheme, but the key point is that it is a direct data clocking process as opposed to a data conversion clocking process.

Jitter was highlighted as a key specification for converter clocks. Similarly, the net effect of a high jitter clock in a wireline communications link can be degraded BER performance. The jitter requirements for network clocks is now examined.

It might be assumed that the jitter requirements for line card clocks are less stringent than those required for wireless transceiver cards. This is certainly true for the majority of the network data rates currently in use. As data rates continue to increase, however, the jitter requirements become increasingly stringent and begin to approach the levels required for many converter applications.

View the PDF document for more information.





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