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3DTV processor cuts need for external FPGA

Posted: 21 Dec 2009 ?? ?Print Version ?Bookmark and Share

Keywords:co-processor? 3DTV? FPGA?

NXP Semiconductors has released the PNX5130 video co-processor enabling 3DTV,

frame-rate conversion (FRC) and local backlight dimming in a single chip. By eliminating the need for external FPGA devices to support 3DTV, NXP is providing a highly cost-effective post-processing solution that will enable manufacturers to bring competitively priced 3D-enabled TV sets to the mainstream consumer market. The PNX5130 enables conversion of all popular 3DTV formats to both line and frame interleaved displays, and is designed for maximum flexibility to support emerging 3DTV standards.

"3DTV is the new product differentiator for home entertainment systems," said Vincent Vermeer, product marketing director for digital TV systems, NXP. "With the growing popularity of 3D movies, we expect to see a much wider range of 3D contentincluding broadcast content and gamesbecome available for TV viewers over the next two years. The challenge for TV manufacturers will be how to make the 3D viewing experience more affordable for the average consumer. The PNX5130 is a critical part of the solutioncombining support for 3DTV, FRC and local LED backlight dimming in a single integrated chip, reducing the total bill of materials."

Flexible architecture
Although 3DTV is still in the early stages of standardization, the flexible architecture of the PNX5130 supports the most popular formats for encodingincluding spatial 3D, temporal 3D and 3D with depthas well as display.

The PNX5130 is able to drive two different types of 3DTV display technologies used today: frame interleave, which it can support at 240Hz, as well as line interleave. In frame interleaved displays, images for the left and right eye are presented sequentially, and require the use of shutter glasses which are synchronized with the alternating frames. In line interleaved displays, passive polarizer glasses are used to filter between odd and even lines, which present different images for the left and right eyes. In addition, the PNX5130 can also generate depth to 2D video or adjust depth to stereoscopic content.

The high-performance PNX5130 video post-processing platform also enables 3DTV with movie judder compensation. Based on the architecture of the PNX5100 platform, which has been widely recognized for its outstanding support of MEMC (Motion Estimation, Motion Compensation), the PNX5130 features the next generation of NXP's proprietary MAPP (Motion Accurate Picture Processing) technology, which combines movie judder cancellation, motion sharpness, and vivid color management in a single device.

PNX5130 video co-processor include 3DTV algorithms and format converters that enable conversion of all popular 3DTV formats to line interleaved (60-/120Hz) and frame interleaved (120-/240Hz) displays. It also features motion sharpness technology and full motion compensated up-conversion (ME/MC) to 1920 x 1080p at 120Hz and 240Hz. The device includes HD halo-reduced movie judder compensation and motion blur reduction as well as integrated local dimming feature for combined local dimming and MEMC applications.

In addition, the co-processor packs wide color gamut mapping; skin tone protection; green, blue and white stretch; sharpness enhancements (2D peaking, LTI, CTI, CDS); and contrast enhancements. It also offers dynamic backlight control and 2D (local) dimming for 120Hz and 240Hz TVs. The PNX5130 will offer integrated Full Motion Estimation for 3DTV starting in Q1 10.

Engineering samples of the PNX5130 are available immediately, while the final software release will be available in Q1 2010.





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