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PCI Express-to-DDR2 SDRAM reference design

Posted: 30 Dec 2009 ?? ?Print Version ?Bookmark and Share

Keywords:SDRAM reference design? PCI Express? FPGA hardware?

This application note introduces the dedicated PCI Express logic block implemented in Arria II GX FPGA hardware and describes the following:
? The hard IP implementation of the PCI Express MegaCore in the Arria II GX device;
? The DDR2 SDRAM high-performance controller;
? The PCI Express protocol;
? Implementing the PCI Express MegaCore with the Quartus II software;
? Verification of multiple IP modules with the ModelSims software.

PCI Express is a point-to-point high-speed serial I/O interface that offers the ability for components to communicate with a much higher level of efficiency. This design conforms to the PCI Express Base Specification, Rev 2.0.

This design represents a sample interface between:

? A device that drives commands to the Arria II GX FPGA using the PCI Express protocol (Root Complex);
? An Arria II GX FPGA (Endpoint);
? An external DDR2 SDRAM memory.

The Altera PCI Express-to-DDR2 reference design is an example of a typical user application that interfaces to an Altera PCI Express MegaCore function.

View the PDF document for more information.

Click here to view related datasheets.





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