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40nm CMOS Serdes achieves 25Gbit/s

Posted: 22 Feb 2010 ?? ?Print Version ?Bookmark and Share

Keywords:Serdes? 40nm? CMOS?

Avago Technologies has achieved serial 25Gbit/s Serdes performance in 40nm CMOS technology. Key differentiators of Avago's Serdes cores are its unique decision feedback equalization (DFE), which results in lower overall power usage, as well as high latency, noise immunity, jitter, and crosstalk performance. Further, due to Avago's modular, multi-rate architecture, its Serdes cores are highly integratable, and channel counts in the hundreds are common.

Offering designers great flexibility, Avago's broad Serdes portfolio is well-suited for optical, copper and backplane applications. Supported standards include PCIe, Fibre Channel, XAUI, CEI-11G, 10GBASE-KR, and SFI.

"Our early achievement of this milestone reflects Avago's ongoing commitment to providing Serdes IP that enables our customers to address the demand for ever-increasing bandwidth," said Frank Ostojic, VP and general manager of Avago's ASIC products division.





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