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Magnetic tunneling enables high-density logic ICs

Posted: 14 Jul 2010 ?? ?Print Version ?Bookmark and Share

Keywords:magnetic tunneling? logic IC? non-volatile memory?

A Japan team claims to have extended a high-performance perpendicular tunneling magneto-resistance (TMR) process to non-volatile logic devices, claiming that device dimensions of 40nm correspond to logic chips with 8Gbit of non-volatile memory.

"When measured in terms of commodity RAM, the size of our device makes it possible to realize an 8Gbit chip with the use of vertical transistors," said Professor Hideo Ohno at Tokohu University. "When these devices are made on top of vertical transistors, the cell dimension can be made 4F?this means that you can accommodate 8Gbit in a 100mm? chip assuming 50 percent cell area."

The tunneling magneto-resistance effect is an extension of spin-valve giant magnetoresistance effect used to record on hard disks. Used as a spin valve, the electron spins are oriented vertically to a thin insulating tunnel barrier, allowing "perpendicular recording" of high-area densities. Since electrons must tunnelthat is, pop out on one side of an insulator and pop back on the other sideTMR is a quantum effect unexplained by Newtonian physics. Similar magnetic tunneling junctions also enable magnetoresistive RAM memories and various reprogrammable magnetic logic devices.

The new perpendicular logic device process was created by Ohno and other researchers at Tohoku University in cooperation with Hitachi Ltd. Their technique makes use of a large perpendicular magnetic anisotropy at the interface between the insulator and its magnetic electrode. As a result, the compact vertical architecture enables bit cells to measure just 4x the square of device dimensionsrather than 64x the square of device dimensions. The result was a 16-fold reduction in the size of logic circuitry using TMR.

According to the researchers, their approach to TMR simultaneously achieves high density, low write current (49?A), tunneling-magneto-resistance ratio of 124 percent and thermal resistance of 350C. That makes the process compatible with the standard fabrication techniques used for logic ICs.

The researchers also report that unlike competing architectures, their devices will be cheap to manufacture (since they use inexpensive noble metals) while promising ultralow power consumption for SoC applications.

Funding was provided by the Japan Society for the Promotion of Science and by the "High-Performance Low-Power Consumption Spin Devices and Storage Systems" program at Tohoku University.

- R. Colin Johnson
EE Times





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