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Magma Design Automation joins Si2's DFMC

Posted: 27 Aug 2010 ?? ?Print Version ?Bookmark and Share

Keywords:EDA? DFM? DRC?

The Silicon Integration Initiative (Si2) welcomes Magma Design Automation as the latest member of the design for manufacturability coalition (DFMC). Other semiconductor supply chain players who are members of the coalition include Cadence Design Systems, IBM, Intel, Mentor Graphics, STARC, Synopsys, Tela Innovations and Texas Instruments.

The group also reports that the DFMC members unanimously approved a 60-day Intellectual Property review period for the first official release of the specification for OpenDFM, a high-level DRC language that can be translated into a variety of proprietary verification languages with no loss of accuracy or performance. OpenDFM describes the patterns for physical verification at a higher level than traditional DRC rules and recent tests indicate it has the potential to reduce the volume of DRC rules by 10X-20X. It is scheduled for release later this year with rapid adoption expected by all major EDA vendors, silicon foundries, and end-user companies.

The next release of OpenDFM will add rules for lithography, chemical mechanical planarization and critical area analysis. OpenDFM provides a compact notation for the description of the patterns of physical verification rules that include conditional rules and ranges of acceptable values.

DFMC's charter is to specify open standards for software interfaces between EDA software tools and manufacturing software. The specification includes standard terminology definitions, semantics and exchange formats for relevant manufacturing information. It also includes standard software API for models describing different manufacturing processes, yield mechanisms and circuit behaviors.

"The DFMC is producing important work for the industry and we are pleased to have all major EDA vendors united in this important effort," said Steve Schulz, president and CEO, Si2.

By joining DFMC, Magma continues to support the industry-wide initiative toward developing a common runset language. "With increasing design rule complexity and number of rules at 65 nm and below, physical verification can become a bottleneck in the delivery schedule," said Anirudh Devgan, general manager of the custom design business unit of Magma. "Our collaboration with other members of the DFMC to define the specification and ensure interoperability of Quartz DRC and Quartz LVS with OpenDFM demonstrates our commitment to providing designers with faster physical verification flows."

Membership in the DFMC is open to all interested parties across the semiconductor supply chain.





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