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Use QDR II SRAM interface for FPGA

Posted: 15 Dec 2010 ?? ?Print Version ?Bookmark and Share

Keywords:Xilinx? Quad Data Rate? Virtex-5?

This application note by Xilinx describes the implementation and timing details of a Quad Data Rate (QDR II) SRAM interface for Virtex-5 devices. The synthesizable reference design leverages the I/O and clocking capabilities of the Virtex-5 family to achieve performance levels of 300 MHz (600 Mb/s), resulting in an aggregate throughput for each 36-bit memory interface of 43.2 Gb/s.

The design greatly simplifies the task of read data capture within the FPGA while minimizing the number of resources used. A straightforward user interface is provided to allow simple integration into a complete FPGA design utilizing one or more QDR II interfaces.

View the PDF document for more information.





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