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DesignCon presents ways to cut design time

Posted: 03 Feb 2011 ?? ?Print Version ?Bookmark and Share

Keywords:design cycles? speeding up design schedules? design tools?

Conferring as a panel at the DesignCon in Santa Clara, California, four designers from Broadcom, Nvidia, Netlogic and Juniper Networks have concluded that designs must satisfy different "good enough" requirements for different markets.

Discussing methodologies that could speed up design schedules, the panelists agreed that design cycles vary across design teams and the design windows for one type of design are markedly different from that of another.

If the design is for backend communications, it needs to be rugged and therefore meet those design criteria that might require today's usual 12 to 18 months. But in designing a consumer phone with features that match and exceed those of competitors, designers need to address a narrower design windowin the order of six monthsto stay competitive with other CE companies.

"As we try to wrap up ever more complex designs in less and less time, the risks that prevent design closure are increasing almost exponentially," said Sunil Malkani, director of IC Design Engineering at Broadcom. "And you can't get away from the fact that verification takes the most time in a design."

"It is hard to generalize on the windows of design," said Ramon Marcias, director of physical design, Processor Group at NetLogic Microsystems. "There is no dramatic way to speed up designs in the back end." NetLogic provides semiconductor solutions for the network enterprise space.

"A week to iterate through your flow to fix a design bug like a bad timing exception or a metastability issue is bearable in a multiyear project," said John Busco, senior manager, Design Implementation at Nvidia, "It doesn't fly in the face of a multimonth project."

Busco was sympathetic to Intel's woes reported this week on recalling its latest chips for a design flaw. "That can be astronomically expensive. I knowwe have been there."

"The most serious 'chip stoppers' are the ones least likely to be caught using commonly used simulation or STA [static timing analyzer]-based techniques," said Ravi Damaraiu, ASIC Director at Juniper Networks. "Using old techniques to catch these problems will no longer cut it when a few days delay may cause you to miss a market window. At Juniper we apply verification to silicon before RTL tape out."


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