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NAND Flash controller supports ONFI 3

Posted: 17 May 2011 ?? ?Print Version ?Bookmark and Share

Keywords:NAND flash? controller IP? FPGA development?

Arasan Chip Systems Inc. has released NAND Flash Controllers supporting the newest Open NAND Flash Interface (ONFI) 3.0 specification. The ONFI 3.0 compliant NAND Flash Controller IP Core is a full featured, synthesisable design that can be easily integrated into any SoC or FPGA development.

Designed to support both SLC and MLC flash memories, it is flexible to use and implement. The controller works with any suitable memory device up to 128Gb from leading memory providers such as Micron, Samsung, Toshiba, Hynix, ST-Micro, and others. Arasan's NAND Flash Controller supports fast transfer modes up to 400MTS with differential signaling on clock and data, and double data-rate transfers (DDR). The IP incorporates all of the features of ONFI 3.0 such as eight chip enables, page sizes up to 8K and ECC up to 64bit with dynamic configuration, warm-up cycles. All ONFI 3.0 commands are supported and the controller is backwards compatible with earlier versions of ONFI.

The IP core supports the ONFI Working Group 3.0 standard and uses differential signaling on the clock and data lines and clocks at any frequency up to 200MHz.

The rapid development of new, high capacity NAND memory devices makes it the preferred non-volatile memory solution for a wide range of products from cellphones, consumer electronics to netbooks. However, this increase in capacity and performance of NAND memories is accompanied with the corresponding increase in memory controller complexity. Arasan's NAND Flash Controller is designed to handle the growing raw error bit rates as NAND memory migrates to finer process geometries by processing information contained in the Extended ECC Information data structure stored in NAND memory. In addition, the controller supports booting directly from NAND memory. The IP core is easily implemented using a generic standard cell based flow combined with delay components that are part of a typical ASIC cell library. According to the company, SoC designers can interface to a variety of NAND memory devices via a standard ONFI interface using the new device.

Arasan offers a 'Total IP Solution' for its NAND Flash Controller IP core consisting of RTL source code, synthesis scripts, test environment and documentation, all backed by Arasan's World-class customer support.





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