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STMicroelectronics completes 20nm chip tapeout

Posted: 07 Jun 2011 ?? ?Print Version ?Bookmark and Share

Keywords:20nm chip? tapeout? design rule checking?

STMicroelectronics (ST), together with Synopsys Inc., has successfully completed the tapeout of its first 20nm technology demonstrator test chip. This marks a critical milestone in the companies' joint R&D efforts to develop a comprehensive design enablement solution for SoC ICs.

Using ST's next-generation 20nm process technology, which was co-developed with its International Semiconductor Development Alliance partners, Synopsys and ST R&D teams built the foundations of the 20nm design environment over the last year and collaborated in standard-cell library routability optimization, coding of complex routing, parasitic extraction and design rule checking (DRC).

Synopsys specializes in EDA, supplying the global electronics market with the software, intellectual property and services used in semiconductor design, verification and manufacturing.

According to STMicroelectronics technology research and development (R&D) group vice president Philippe Magarshack, ST has been at the forefront of advanced process technology development as a joint development partner of the ISDA alliance, working closely with Synopsys to enable the readiness of key components in the company's 20nm design flow.

He said ST's close R&D interaction with Synopsys enabled the company to validate and optimize the implementation solution, bringing it closer to the silicon chip's release date in the second quarter of this year.

Meanwhile, Synopsys senior vice president and implementation group general manager, Antun Domic, said STMicroelectronics has been the company's valued partner in new technology development for a long time and that their latest achievements in 20nm design enablement show that their close collaboration "has borne fruit," proving that they can provide critical components at the right time to meet the 20nm transition needs.

Domic said Synopsys will continue collaborating with ST to achieve a production-ready environment for high-quality 20nm design implementation and that as part of this effort, Synopsys will further strengthen its R&D presence in France through its European R&D team which has already deployed more than 400 engineers across 15 countries.





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