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Test solution automates 3D IC deployment

Posted: 09 Jun 2011 ?? ?Print Version ?Bookmark and Share

Keywords:automated? test solution? 3D-IC?

Belgium-based nanoelectronics research institute Imec International and electronics design firm Cadence Design Systems Inc. have developed an automated test solution for design teams deploying 3D stacked ICs (3D-ICs).

According to the two companies, their design-for-test (DFT) and automatic test pattern generation (ATPG) technology caters to electronics companies that have turned to 3D-ICs to enhance circuit density and performance. It works by making it easier for the users to test 3D-ICs with "through-silicon via" (TSV) functionality, ensuring that the stacked system works as planned.

They added that the technology is a result of a comprehensive research program

on TSV-based 3D-IC design. Insights gathered from the program prompted imec to extend the DFT architecture for conventional (2D) ICs with several novel (patent-pending since Q1 2010) features.

The 3D DFT architecture is based on the concept of die-level test wrappers which enables testing of chips with TSVs and micro-bumps during pre-bond test stacking, mid-bond test stacking and post-bond test sacking, including after packaging.

Cadence senior architect Brion Keller said the new DFT solution is a testament to the company's commitment to the emerging area of 3D-IC.

"Over the past two years, we've introduced 3D-IC TSV and silicon interposer capabilities, and, just three months ago, the industry's first wide I/O memory controller IP solution, with a robust 3D-IC integration environment. Collaboration is an essential element of effective Silicon Realization and the EDA360 vision we adhere to, and this initiative with imec demonstrates why," Keller said.

Imec principal scientist Erik Jan Marinissen said the 3D-IC and TSV technology could help electronic companies create new-generation of super chips.

"The Imec-Cadence offering inserts DFT structures with minimal area overhead, and the ATPG method helps drive toward zero manufacturing defects on the TSVs. This unique offering reduces risk and promotes cost-effective fabrication of these chips," Marinissen said.

To create the design flow automation for adding 3D-enhanced IEEE 1500-based die wrappers to existing chip designs, the two companies enhanced the existing IEEE 1500 wrapper insertion support in the Cadence Encounter RTL Compiler synthesis product.

According to the two companies, initial result on customer designs showed that the 3D DFT structures could be implemented with negligible area cost at about 0.2 percent





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