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Software promises speedier FPGA design

Posted: 15 Dec 2011 ?? ?Print Version ?Bookmark and Share

Keywords:design software? FPGA? power-sensitive?

Lattice Semiconductor Corp. (LSCC) has unleashed its Lattice Diamond 1.4 software that the company says is ideal for Lattice FPGA products. The design software boasts usability enhancements that make FPGA design exploration easier and cuts time to market, added the company.

The Lattice Diamond 1.4 software enhances support for the MachXO2 PLD family by providing final production timing, power models and bit-streams for the entire family. This includes the latest wafer-level chip scale packaged version of the LCMXO2-2000U and LCMXO2-1200U devices that are geared for very high volume, cost- and power-sensitive applications. Moreover, customers can begin designing with the low cost, low power mid-range LatticeECP4 FPGA family, noted LSCC.

Lattice Diamond 1.4

The Lattice Diamond design software targets high volume, cost- and power-sensitive applications.

The design environment enables users to easily explore design alternatives as they target the type of applications ideally suited for the MachXO2 PLD family. Lattice Diamond 1.4 software includes final data for timing, power, package and bitstream based on the actual silicon characterization of all the MachXO2 devices, stated the company. The final simultaneous switching output (SSO) data is available for all packages (except the wafer-level chip scale package of the LCMXO2-2000U).

Lattice Diamond 1.4 software provides a report of device resources used by level of design hierarchy following either the synthesis or the map step (a process that maps the synthesis output to the device resources). Device resources can therefore be reported out as both logical (registers) and physical (slices) elements. This feature helps users quickly understand what parts of their design are using scarce device resources so that they can optimize the design for the targeted device. This information can be exported to a text or a CSV file to enable analysis in other tools.

To improve timing closure productivity, users can now set up the multiPAR placement and routing tool to stop after either trying a maximum number of seeds (or starting points) or when the last seed run has resulted in timing closurewhichever comes first. In order to perform design exploration even faster, these multiPAR tasks can now be distributed to run in parallel on computers with a multicore CPU.

In addition, users can employ the Run Manager tool to process multiple implementations (or design structures) in parallel and accelerate timing and utilization results for these multiple implementations. Users can individually control the maximum number of implementations and multiPAR processes that can be run simultaneously. With Lattice Diamond 1.4, LSCC stated that users can also compare run reports of multiple implementations side by side and easily determine the best implementation for their design.

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