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Advances in 3D-IC testing

Posted: 03 Feb 2012 ?? ?Print Version ?Bookmark and Share

Keywords:3D-IC? through silicon vias? post-bond test?

Three-dimensional integrated circuit (3D-IC) systems has the potential to provide significant improvements in performance, power, functional density, and form factor over other packaging integration techniques. Despite substantial progress toward realizing 3D-IC systems, a variety of design, manufacturing, packaging, and testing issues still need to be addressed before cost-effective, high-volume production can be achieved. In this article we will focus on the test challenges and solutions, highlighting a design-for-3D-test architecture and implementation flow developed by researchers at Industrial Technology Research Institute (ITRI) based on the Synopsys test solution.

2.5D before 3D
Advances in manufacturing and packaging technologies have already brought "2.5D" platforms within reach of early adopter design teams: 2.5D IC integration offers the potential to deliver a tighter form factor than standard systems-in-package by mounting multiple dies atop a common electrical interface, called a silicon interposer, and connecting them together with wires that run through the interposer [1]. The system I/Os are connected to the underlying package substrate using vertical through silicon vias (TSVs), essentially cylindrical metal posts that extend partway through the interposer (figure 1).

However, when it comes to delivering on the integration benefits mentioned above, 3D die stacking [2] holds the greatest promise. With this approach, TSVs are etched deep into the substrate and the wafers thinned down to less than 50 microns. Many dies can then be stacked vertically on top of each other and connected together by TSVs (figure 2). A combination of the two techniques resulting in a heterogeneous system of multiple die stacks would utilize a silicon interposer to connect all the bottom dies in the same way as 2.5D-IC packages.

Figure 1: 2.5D configuration with silicon interposer.

The design of the first 3D-IC systems is now underway, thanks to the development of standards by organizations such as IEEE, JEDEC, SEMI, and Si2 in cooperation with semiconductor and electronic design automation companies. For example, in October 2011 Samsung and Micron Technology announced the creation of a consortium to accelerate industry collaboration for the development of an open interface specification for Samsung's Hybrid Memory Cube, which delivers "unprecedented system performance and bandwidth" in part by employing vertically stacked memories connected through TSVs. In spite of early progress, a range of technical obstacles still need to be overcome to achieve cost-effective, mass production of 3D-IC systems, and we now turn to the challenges confronted when testing them in a high-volume setting.

Figure 2: 3D configuration with face-to-back bonding of two stacked dies connected by TSVs.

Testing in 3D
One basic approach to 3D-IC testing involves performing a post-bond test after each die has been bonded to the stack. The goal is to test portions of the system that could have been damaged during the bonding process. Because it is not viable to "un-bond" a die subsequently found to be defective, one study [3] maintains that performing a separate pre-bond (i.e., standalone) test to identify a Known Good Die (KGD) for stacking is more cost-effective than relying solely on post-bond testing to identify a defective die that has already rendered the entire system defective.

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