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Use FPGAs to harness potential of flash for enterprise apps

Posted: 03 May 2012 ?? ?Print Version ?Bookmark and Share

Keywords:Enterprise storage subsystems? Programmable State Machine? FPGA? flash?

FPGAs also now feature soft and hardened IP cores, such as memory controllers, embedded processors and transceiver blocks, that further enhance performance, enrich functionality and improve efficiency. Finally, advances in PLD packaging accommodate a generous number of high-speed I/O ports as well as general-purpose I/O pins.

Programmable state machine for flash cache
Memory array maker, Violin Memory Inc., outlines the following high-level attributes of a memory array that scales cost-effectively and addresses the needs of next-generation, 24x7 enterprise data centers:

Performance: Seeks an order-of-magnitude improvement in latency and I/O operations per second (IOPS) over that attained by HDD, i.e. sub-millisecond latencies, and >200K IOPS per shelf, to better match processors.

Cost: Deploys solid state memory, but at significantly reduced cost in terms of both cost per GB and cost per I/O.

Reliability: Ensures no enterprise data are lost (via RAID algorithms) and that systems can be serviced without downtime.

These attributes can be realized in new breed of storage array based on low cost per GB NAND flash memory. The architecture features two levels of flash functionality, flash control (vFLASH) and flash RAID (vRAID). The flash controller leverages flash technology read, write, erase operations and error conditions at the bit, block, plane and chip level in a flash translation layer. VFLASH functionality includes log-structured data layout and flash management "garbage collection" to keep space freed up. The RAID controller for flash memory should go beyond traditional RAID-1 and RAID-5 algorithms to address the unique characteristics of flash. For example, a 4+1 parity model is much more efficient and has lower latency than traditional algorithms, and also can cope more effectively with failures without requiring module replacement.

Both flash and RAID control can optimally be implemented in FPGA technology as illustrated in figure 2. By implementing key algorithms in silicon-based state machines rather than the traditional microprocessor/software approach, significantly lower latency can be achieved. And, as mentioned previously, FPGA-based implementation results in a very flexible design that accommodates the rapid evolution of flash and associated features. A new design can be brought to market, and new opportunities be explored, very rapidly, at very low cost.

Figure 2: Block diagram of a memory subsystem.

Also, by leveraging FPGA features such as memory controllers, transceiver blocks and high-speed interfaces to memory and PCIe cards, a highly optimized system can be brought to market in a matter of days or weeks, much faster than traditional approaches.

New paradigm for enterprise storage
Enterprise storage systems today require the performance and cost advantages of flash memory to be competitive. The unique design challenges associated with flash, such as ensuring data integrity and dealing with emerging memory types and evolving standards, are readily addressed via deployment of FPGA-based PSM for memory management and I/O. The combination of FPGA technology and flash memory gives storage system architects a powerful means to attain the performance, while ensuring the system integrity, scalability and adaptability, required of even the most demanding workloads.

About the author
David McIntyre manages the Computer and Storage Business Unit at Altera Corporation. His responsibilities include driving top tier customer growth with initiatives and solutions.

With 20 years of experience at semiconductor and systems companies, David has held various engineering and marketing management positions including a director of strategic marketing post for the IBM Storage Systems Division.

To download the PDF version of this article, click here.


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