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Intel finFETs show variability, need SOI for scaling

Posted: 08 Jun 2012 ?? ?Print Version ?Bookmark and Share

Keywords:finFET? SOI? chip manufacturing? 2nm? Ivy Bridge?

Cross-sectional images from Chipworks Inc. has showed Intel Corp.'s 22nm FinFETs showing physical variability. Because of this, EDA company Gold Standard Simulations Ltd (GSS) has attempted to model electrical characteristics of various examples.

One conclusion drawn by Prof. Asen Asenov, CEO of GSS is that Intel may need to turn to silicon-on-insulator (SOI) wafers to scale its FinFETs below 22nm. This may also have implications for foundries that are yet to introduce FinFET technology into their chip manufacturing processes.

Analysis reveal Intel finFETs' triangular structure
An analysis by Chipworks revealed microscope sections of some parts of Intel's 22nm Ivy processor showing that the FinFETS are in fact trapezoidal, or almost triangular in cross-section.The triangular section is markedly different to the idealized rectangular section that Intel had shown previously in 2011.
Read more of Chipworks' analysis here.

GSS has already done some TCAD simulation of FinFET and posted findings in a blog that discussed the fact that at 22nm Intel's FinFETs are trapezoidal rather than rectangular in cross-section.

The latest GSS blog seeks to compare the on-current of differently shaped FinFETs. It points out that in logic applications multiple fins are connected in parallel, resulting in an averaging of their characteristics, but in SRAM circuits the variability in the single fin is a key characteristic and performance limiter.

The characteristic dimensions of three FinFETs were fed into the GSS Garand simulator and revealed that at 22nm, nature appears to have worked to Intel's advantage. "Despite significant differences in the shape of the three fins, the difference in the on-current is within a 4 percent range," the blog states.

Intel FinFETs

TEM images of three Intel FinFETs with the GARAND simulation domain overlaid.
Source: GSS

"Compared with process variation across the chip or across the wafer 4 percent is small. But it is additional variation," Asenov told EE Times. He added that the simulation revealed that FinFET process technology is complex and difficult to implement, partly because of the lack of a planarization process that can level-up shallow trench isolation oxides between transistors. One result of this is that bulk FinFET heights can vary.

Asenov admitted that a number of assumptions have to be made to allow the simulations to run. It is assumed that the fin itself is virtually undoped but there is a punch-through stopper dopant region beneath the fin. "We don't know about dopant profiles and strain, but we have tried to make favorable assumptions," he said.

Intel FinFETs

Dependence of on-current, ION, on gate length.
Source: GSS

GSS has included results for simulations of rectangular cross-section FinFETs with 10nm and 8nm widths hinting at where the company thinks Intel must go next. "If you can make them [FinFETs] rectangular you will gain significantly in terms of performance, about a 20 percent gain."

Asenov said that moving from bulk FinFETs to FinFETs constructed in SOI wafers could solve a number of problems. "The buried oxide layer means you don't have the problem of filling trenches. The height of the fin is determined by the depth of the silicon above the oxide."

He added: "I think Intel just survived at 22nm. I think bulk FinFET will be difficult to scale to 16nm or 14nm. I think that SOI will help the task of scaling FinFETs to 16nm and 11nm. Of course the wafers are more expensive, but you save money with less processing."

Researchers from GSS and the University of Glasgow published a paper at the International Electron Devices Meeting of 2011 dealt with FinFETs implemented in SOI wafers and how they could meet low statistical variability requirements of 11nm CMOS.

- Peter Clarke
??EE Times





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