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Boost electronics system quality through IC supplier-customer cooperation

Posted: 23 Jul 2012 ?? ?Print Version ?Bookmark and Share

Keywords:electrical over-stress? electrostatic discharge? no-trouble-found?

FPPM reduction can only be achieved collaboratively, through information exchange. Given the present trend of continuously increasing complexity in electronics, quality levels that were good-enough yesterday are no longer sufficient today. The new era of sub-FPPM (hence FPPB C Failing-Parts-Per-Billion) quality is about to commence.

Rootcause analysis throughput time reduction
Because in customer support services time is money, rootcause analysis throughput time is a key parameter for any quality professional. Reducing analysis throughput time helps the entire supply chain to eliminate unnecessary cost and increase customer satisfaction.

The benefits from this approach can be summarized to be:

Reduction of quality costs: The amount of bottom line savings increases exponentially as one moves upwards along the supply chain from the IC supplier to the car maker. Keep in mind, the costs of poor quality related only to EOS/ESD could easily reach 5% of the turnover; for a 200M? business the actual losses due to EOS/ESD can reach the 10M?, a considerable amount. Similar amounts are spent for servicing NTF issues.

Freeing-up a considerable amount of resources: Hence resources can be allocated to more profitable activities like R&D, or process improvements. A low complexity EOS/ESD issue can keep an R&D team busy for approximately 400 man-hours whereas NTF rootcause analysis can end up costing 1,000 man-hours.

Acceleration of the PDCA loop: By optimizing throughput time and efficiency, rootcause analysis can happen close to the source (to the environmental conditions in which the failure originally appeared), leading to an acceleration of the complaint-handling PDCA loop. This creates a lean infrastructure on which to perform rootcause analysis extending from the IC manufacturer to the car maker.

Electrical over-stress and electrostatic discharge
The field of EOS/ESD is a complex one, mainly due to the multiple mechanisms that may lead to such events. To assure that no latent damaged parts are ever delivered to customers, IC manufacturers must spend a continuously increasing effort in screening outlying devices during wafer-test (WT) and final-test (FT) using advanced techniques like for instance the Moving Limits. In the frame of the EOS/ESD/NTF program, companies can take this one step further by teaming up with PCB module makers to reach even lower zero-defect targets.

In the frame of this cooperation the following points are addressed:

Development of EOS/ESD robust systems: Cooperation on EOS/ESD starts during the design phase in the form of module design and layout reviews. EOS/ESD is a failure mode that depends strongly on the design of the module. The latter should be able to resist all types of EOS, such as ESD (electrostatic discharge), EMI (electromagnetic interference), LU (latch-up), OVS (overvoltage stress), or any other type of electrical misuse [see Ref. 1]. These are aspects to be considered during design phase since the protection strategy and components have to be timely chosen.

Troubleshooting manufacturing facilities: Under this category are found EOS/ESD process capability investigations of customer manufacturing facilities. Although manufacturing facilities may be designed to follow the IEC61340 or S20.20 ESD recommendations, ESD control target levels have to continuously be updated (reducing trend) for the assembly facilities to be able to cope with (1) the continuous miniaturization of the IC manufacturing processes and (2) the increase of the package dimensions to accommodate more complex integrated systems [see Ref. 2].

Design for testability for EOS/ESD: Being able to verify whether a module has been pre-damaged during the module assembly process, specific leakage current tests can be included in the in-circuit test (ICT) or end-of-line test (EOLT) during module assembly. The data can then be used to perform advanced screening as, for instance, Part-Averaging-Testing (PAT) as recommended by the Automotive Industry Council (AEC) in the AEC-Q100 specification or Moving Limits, which is a more efficient technique.

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