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Improve SoC yields with diagnostic and repair tools for embedded memory

Posted: 09 Aug 2012 ?? ?Print Version ?Bookmark and Share

Keywords:system-on-chip? embedded memory test? 3D-ICs?

Memory plays a vital role in the functioning of embedded systems. Indeed, embedded memories in system-on-chip (SoC) devices can account for 50% or more of chip area. Implemented using aggressive design rules, embedded memories tend to be more prone to manufacturing defects and field reliability problems than any other core on the chip. To improve yield and reliability in embedded devices, manufacturers need solutions that simplify fault detection, process improvement, and repair at the manufacturing level and in the field while minimizing cost and impact on functionality.

New systematic defects are often manifested as yield-limiting faults resulting from known factors such as reduced feature sizes. Additionally, the use of high-density integration and packaging technologies such as 3D-IC, which require complex manufacturing processes and have associated physical access limitations, further compounds the problem. These new and emerging challenges make it critical that embedded memory test and repair solutions keep up with technology advances in order to consistently provide superior test quality and yield optimization. This article will describe embedded memory test solutions, including fault detection in very deep submicron technologies, repair at the manufacturing level, and diagnosis for process improvement and field repair capabilities, that address today's design yield and reliability needs.

Figure 1: Embedded memories account for half the die area of a typical SoC today. Predictions are that this will increase to 70% of the die area by 2017.

Keeping up complexity
Today's demanding applications require SoCs that are bigger and faster that are more area, timing, and power sensitive than ever before, resulting in a shift from the logic-dominant chips of the past to memory-dominant ones. Figure 1 shows embedded memory projections from Semico Research Corporation. In 2008, embedded memories accounted for more than half of the die area in a typical SoC. It's predicted that the amount of space they occupy on the die will continue to increase, reaching up to 70% by 2017.

Applications that require lots of memory are served by designs that embed large numbers of memory bits per chip, creating more powerful SoCs, but this has the associated problems of increased die size and poor yield. As design applications require more memory, it is essential to implement a comprehensive embedded memory test, repair, and diagnostic solution to help achieve high yield.

In addition to needing the capability to deal with increasing numbers of on-chip memory instances, the embedded memory test solution also must be able to handle aggressive design specifications, such as hierarchies, size, performance, area, and power consumption. As embedded test solutions often have a negative impact on performance, it is important that high-performance cores be built with carefully planned memory BIST MUX logic and an integrated memory test bus to minimize these effects. The bus consists of pipelining, latency, and setup for the memory signals of all the memory instances in the core and eliminates the need for a traditional BIST wrapper for each memory.

An embedded memory test solution will interact with this test bus and add the required logic to use the test bus interface for embedded memory test. Additionally, an effective embedded memory test solution will understand the functional pipelining with predetermined controllability and observability logic on the timing-sensitive datapaths, and it will have the flexibility to add the required number of pipeline stages on the memory BIST paths to meet the performance targets of the design. To further address design complexity, a test and repair solution that is integrated with embedded memories, with most of the timing-critical BIST wrapper logic hardened in the memories, makes it possible to achieve faster design closure while meeting the performance, power and area characteristics of the design.

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