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ARM's new on-chip interconnect delivers Tb/s throughput

Posted: 12 Oct 2012 ?? ?Print Version ?Bookmark and Share

Keywords:System IP? CoreLink CCN-504? CoreLink DMC-520? dynamic memory controller?

ARM has released what it says is an advanced system intellectual property (IP) that can deliver up to 1Tb of usable system bandwidth per second. The ARM CoreLink CCN-504 cache coherent network can enable SoC designers to provide high-performance, cache coherent interconnect for 'many-core' enterprise solutions built using the ARM Cortex-A15 MPCore processor and next-generation 64bit processors, added the company.

ARM has also unveiled the ARM CoreLink DMC-520 dynamic memory controller that has been designed and optimised to work with the CoreLink CCN-504. The dynamic memory controller provides a high-bandwidth interface to shared off-chip memory such as DDR3, DDR3L and DDR4 DRAM.

CoreLink CCN-504 enables a fully-coherent, high-performance many-core solution that supports up to 16 cores on the same silicon die. It also allows system coherency in heterogeneous multi-core and multi-cluster CPU/GPU systems by enabling each processor in the system to access the other processor caches. This reduces the need to access off-chip memory, saving time and energy, which is a key enabler in systems based on ARM big.LITTLE processing, a paradigm that claims to deliver both high-performance, required for content creation and consumption, and extreme power efficiency for extended battery life.

The CoreLink CCN-504 supports both the current-generation high-end Cortex-A15 processor and future ARMv8 processors and is the first in a family of network-based interconnect products planned by ARM.

The CoreLink CCN-504 cache coherent network includes integrated level 3 (L3) cache and snoop filter functions. The L3 cache, which is configurable up to 16MB, extends on-chip caching for demanding workloads and offers low latency on-chip memory for allocation and sharing of data between processors, high-speed IO interfaces and accelerators. The snoop filter removes the need for broadcast coherency messaging, further reducing latency and power, noted ARM.

First to avail of the CoreLink CCN-504 license are semiconductor design firm LSI and Calxeda, a developer of ARM-based processors and software for low-power servers. (See LSI, Calxeda receive licenses for ARM's on chip link .) Sampling in partner products starts in 2013.





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