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ST, Soitec roll 28nm FD-SOI CMOS process thru CMP

Posted: 23 Oct 2012 ?? ?Print Version ?Bookmark and Share

Keywords:FD-SOI CMOS? CMP? Fully Depleted Silicon-On-Insulator?

STMicroelectronics, Soitec (Euronext) and Circuits Multi Projets (CMP) have revealed that ST's CMOS 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) process, which uses silicon substrates from Soitec, is available for prototyping through silicon brokerage services provided by CMP. According to the companies, the solution targets universities, research labs and design companies.

The introduction in CMP's catalogue of ST's 28nm FD-SOI CMOS process builds on the successful collaboration that has allowed universities and design firms to access previous CMOS generations including 45nm (introduced in 2008), 65nm (introduced in 2006), 90nm (introduced in 2004), and 130nm (introduced in 2003). CMP's clients also have access to 65nm and 130nm SOI, as well as 130nm SiGe processes from ST.

Since CMP started offering the ST 28nm CMOS bulk technology in 2011, some 60 universities and microelectronics companies have received the design rules and design kits and 16 ICs have already been manufactured, boasted the company.

The CMP multi-project wafer service allows organisations to obtain small quantitiestypically from a few dozens to a few thousand unitsof advanced ICs.





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