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Electrically-aware design enhances AMS ICs

Posted: 27 Nov 2012 ?? ?Print Version ?Bookmark and Share

Keywords:analogue/mixed-signal? observability? Electromigration?

One of the most challenging aspects of analogue/mixed-signal (AMS) IC design is uncertainty in electrical behaviour and reliability. While uncertainty can be a problem at any process node, it is particularly pronounced at the advanced nodes that will be needed to meet demands in high-growth areas like mobile computing. In conventional custom IC design flows, there is little observability into the electrical impact of physical design decisions until the layout is complete and design intent can be verified through parasitic extraction and circuit simulation. The combination of electrical uncertainty combined with increasing sensitivity of AMS designs to parasitics and layout dependent effects can result in significantly higher turn-around times and more conservative designs that sacrifice performance for reliability. To mitigate the risks associated with moving to advanced nodes, IC design teams will require EDA solutions that reduce electrical uncertainty and ensure design intent is preserved during custom design.

An ideal solution would electrically verify the performance and reliability of every single physical design decision so the layout is electrically correct by construction and optimised to meet the design intent. This article describes a new EDA methodology, called electrically-aware design, where every physical design decision regarding placement and routing can be analysed or visualized in terms of its impact on electrical performance and reliability. While this methodology can be applied to a number of use models, this article focuses on reducing the uncertainty associated with electromigration (EM)-related reliability, an increasingly serious problem at advanced process nodes.

Design productivity and time to market are highly dependent on reducing uncertainties introduced during physical design. Uncertainty in the electrical behaviour and reliability of analogue/mixed-signal chips results from the sensitivity of analogue devices to variability and the complex parasitic interactions among devices and interconnect. Additional uncertainty results from manufacturing and layout-dependent geometric dimensions, orientations, and the distances between adjacent devices. In addition, the ability to create identical devices is often critical to meeting electrical performance and design intent from a circuit perspective.

Design choices may be used to minimise variation and maximise performance, but understanding which choice is appropriate for a given context can be a complex undertaking. In conventional custom design methodologies, designers are forced to make physical design decisions with little or no way to immediately measure the electrical consequences of their decisions. Verification through simulation or reliability checking conventionally occurs when the physical design is complete, often requiring multiple design iterations to achieve successful silicon. The lack of electrical observability until the very end makes it harder to identify the cause of the unwanted behaviour and reduces the set of potential fixes.

Electrically-aware design will provide designers and layout engineers with immediate electrical feedback as layout shapes are created, and it will do this in-design. This in-design verification will also allow the electrical intent of the designer to be fed forward to ensure that each step in physical design meets their desired electrical intent. New methodologies will be required to enable incremental extraction and electrical analysis, and to provide observability into the consequences of design decisions as each decision is made. Electrically-aware design improves productivity by reducing the number of design iterations and the overall uncertainty that leads to overly conservative designs and reduced in-silicon performance and profitability.

Electromigration and its causes
Electromigration (EM) effects can seriously damage interconnect wires and vias, having an adverse impact on IC reliability. Electrically-aware design provides new in-design methodology opportunities for EM verification, and the same general methodology could be applied to a range of in-design electrical checking and simulation solutions.

EM is the transport of material in a solid conductor that results from collisions between the flow of electrons and metal atoms in the interconnect. Proportional to the current per unit area, the continual movement of metal atoms from their lattice position can lead to a degradation in performance as the resistance of the interconnect increases. At some point the wire eventually fails, creating an electrical open (void) or short connection (hillock) downstream.

The dominant factor in determining mean time to failure (MTTF) is the current density. Since current density depends on the wire geometry, it cannot be determined until the routed net is generated. Given that the width of the wire or via is a variable, designers need to know whether the current flowing through that particular area has exceeded the maximum allowed current. The maximum current limit for a given geometry is expressed as rules that every wire segment or via must adhere to for a specified operating or maximum temperature. This set of rules is contained in a technology file that is computed and distributed according to each process technology specification.

With the aggressive scaling of interconnect geometries at advanced technology nodes, the EM effects are dependent not only on the local current density of a geometric wire segment or via, but also on the homogeneity of the current flow through a region. As such, current density limits or rules vary based on not just each geometric dimension of the wire segments and vias, but on the geometries of the connecting wires and vias as well.

There are additional complications. There is a minimum length below which the net won't fail due to EM, commonly referred to as Blech length. This adds another dimension to the problem of sizing a wire for EM. The EM rules for a metal layer are specified in buckets for different limits based on the width and length of shapes on the layer. Without assistance from an EDA tool, it would be cumbersome for a layout engineer to route nets on various layers and account for the ever-increasing number of EM rules associated with these buckets.

The EM rules become even more complicated when vias and contacts are considered. Traditionally, single via or contact cuts had a current density number associated with them, while clusters of vias would have more relaxed rules. At advanced technology nodes, a single via or contact will have different current density limits based on different shapes (e.g. square or rectangular). This issue is compounded when additional conductors are connected to the via(s) and the current density limits can change based on the width and length of the connecting conductors.

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