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Electrically-aware design enhances AMS ICs

Posted: 27 Nov 2012 ?? ?Print Version ?Bookmark and Share

Keywords:analogue/mixed-signal? observability? Electromigration?

This behaviour is illustrated in figure 1 with three interconnect examples that are based on different widths and lengths of connecting wires. All three have different current density (EM) limits. Each has an upper and lower interconnect wire connected through the same via shape, but each example forms a different geometric profile where the length or width dimensions of the interconnect differ.

The leftmost connection in the figure has the shortest lengths in the dimension of the upper and lower interconnect wires, with the result that the connecting via cut has the highest current density limit and thus can carry the most current without violating the limit. The middle connection has the same interconnect wire width as the left one, but the wire lengths of the upper and lower interconnect are much longer. The impact is that the current density limit for the via cut is lower than the left example. As such, the middle connection can carry less current and remain within the EM-related reliability limits.

Figure 1: Geometric-based rules require proximity of current calculations with conductor (net) geometry.

In the rightmost connection in figure 1, the upper and lower interconnect lengths are the same but the width of the wires coming into the via are reduced. The result is that the current density limit for the via cut is significantly reduced from the middle and leftmost examples. Note that in all three examples the via geometry is the same and, if examined without any context of the surrounding wire geometry, it is impossible to know which current density limits to apply.

In addition to the geometric properties of the interconnect, the underlying topology of the routing can also significantly change the distribution of current flow and, subsequently, current densities. Thus the same geometric description (such as a specific width and length of a wire) may or may not meet pre-specified current density limits, depending on the topology of the surrounding interconnect.

Figures 2 and 3 highlight a case where the incoming current to the MOS device may be connected to the strap in two different locations. In figure 2, the current is sourced into one side of the M2 strap, which results in a large amount of current flowing through the strap to reach the M1 vertical finger connections on the other end. Colour coding is used to indicate the proximity of that wire location to the specified current density limit. In this case, the green coding indicates that the current is far from reaching the limit; red coding represents that the current is over the limit for that particular wire segment.

Figure 2: Connection to MOS device resulting in current density violations with highlighted circle noting the current density violations in finger connections to the source.

In figure 3, the incoming current is connected to the middle of the M2 strap and, as such, the current is distributed more evenly throughout the source vertical connections (fingers). As the colour coding indicates, the current limit is not exceeded, even though the geometric properties of the fingers, strap, and incoming wire are very similarthe primary distinction being where the connection has been made. This example also illustrates why it is difficult to specify current-correct routing decisions a priori without knowledge of the underlying topology. This rather simple case was chosen to illustrate the problem, but there are many such cases where the correction to the routing topology is not straightforward, often resulting in a cycle of layout modification, extraction, and analysis.

Figure 3: Alternate connection to same MOS device from previous figure, resulting in no current density violations.


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