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Electrically-aware design enhances AMS ICs

Posted: 27 Nov 2012 ?? ?Print Version ?Bookmark and Share

Keywords:analogue/mixed-signal? observability? Electromigration?

The prior examples illustrate just some of the complexities of designing at advanced nodes. As the rules become more geometry-dependent, it will become increasingly difficult to know which wire segments or vias to fix and how to do so without creating another violation. The following paragraphs propose an electrically-aware design methodology for in-design EM checking that improves productivity while reducing the risk and uncertainty of moving to advanced nodes.

Electrically-aware, "in design" verification
As shown in figure 4, the in-design flow begins with creation of a schematic that is simulated and modified to meet the designer's specifications. After the ideal, pre-layout simulation is completed, the currents at each terminal are saved. A testbench setup is configured to generate the average, RMS, and peak currents necessary for EM checking.

Figure 4: In-design EM verification methodology allows for current densities to be computed and checked as interconnect is incrementally created or modified.

After device creation and placement, routing is initiated. For a given interconnect geometry to be routed, the EM limits should verify that it is below the maximum current or current density allowed for each segment of the net. To solve the current flow, parasitics need to be extracted as the net is routed and sized. The extracted parasitics are then used to solve current distribution throughout the wires and vias that constitute a net, with extraction and current solving occurring as the net is created.

Foundries create and maintain EM-related current density limits to ensure reliability of the manufactured device over years of operation at nominal and elevated temperatures. These limits are provided in a technology file and, as discussed above, are growing increasingly complex with geometric dependencies. During layout creation, the limits from the techfile are loaded and made available for in-design verification. The current limits and the solved currents for each geometric shape or set of net shapes are checked as layout edits are made.

Use models for electrically-aware, in-design verification and optimisation fall into three basic categories: manual, assisted, and automatic. It is likely that a manual use mode will be adopted by users first until they are confident that in-design solutions provide accurate problem detection and correction. The results can be displayed in real time as colour-coded overlays on the layout (figures 2 and 3), or a threshold may be set where only violations are shown.

When violations are identified in the GUI, the user can simply click on the net and resise the wire. Incremental electrical analysis immediately checks the edit, and when the wire is sufficiently wide, the display is updated accordingly (as indicated with the green overlay). Sometimes resizing may not be sufficient or desirable. In those cases, movement of the route location may be necessary, as shown in figure 3. Once the net passes verification, the user can move to the next net to be routed.

In the assisted use mode, once a current density limit violation is identified, the tool will compute and display a suggested fix such as "increase wire width by 100%." The user would have the option to review and approve fixes individually or simply approve all. As the user becomes more comfortable with the suggested modifications from the tools, in-design solutions can drive more automatic wire sizing and routing changes during the routing process. This approach is often referred to as current-driven routing, which may take the form of a feed-forward approach (a topology editor and wire size selection are used to select net properties prior to physical routing), or a feedback approach (an optimisation loop and cost function are used to iterate after the net is routed until the acceptance criteria are met).

Conclusion
For analogue/mixed-signal chips, the reduction of uncertainty during physical design will similarly reduce overly conservative design practice ('practise' when verb)s and improve return on investment in terms of in-silicon performance and profitability. Electrically-aware, in-design verification methodologies will reduce uncertainty through electrical assessment, verification, and optimisation of each incremental physical design decision. One of the largest contributors to electrical uncertainty is the current density limits imposed by electromigration, and most believe these limits will become even more complex at 20nm and beyond.

In this article, new methodologies have been proposed to incrementally extract parasitic and check (cheque for banks) current-related limits as each net is routed. Initial solutions will likely identify solutions and provide users with assistance in resolving any problems. As users become more confident in the ability of in-design solutions to automatically correct such issues, the introduction of current-driven routing methodologies and solutions will be addressed. These solutions will evolve towards the ultimate goal, which is an EDA solution that generates layout that is electrically correct by construction and minimises turnaround time for analogue/mixed-signal designs.

About the authors
David White received a Doctor of Science Degree in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology in 2001. He currently directs R&D for Virtuoso Electrically Aware Design products at Cadence Design Systems in San Jose, California. He joined Cadence in 2006 through the acquisition of Praesagus, a software company he co-founded in 2001 and where he served as Chief Technology Officer until the merger. Dr. White has served as a member of the Advisory Board for the National Science Foundation (NSF) in Washington D.C. as well as advisory boards at MIT and early stage companies.

Akshat Shah received his Bachelors of Science Degree in Electrical and Computer Engineering from Carnegie Mellon University and his Masters in Business Administration from the University of Pittsburgh. Akshat is currently the Product Engineering Director for Virtuoso platform. His team is responsible for the Virtuoso Front-End, the Electrically Aware Design flow and the 20nm Advanced Nodes Flow. He joined Cadence thru the Neolinear acquisition in 2006 where he was a Product Engineer and drove the NeoCircuit and NeoCell products which are now part of the Virtuoso platform.

To download the DPF version of this article, click here.


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