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Globalfoundries consider SSRW tech as 3rd option

Posted: 20 Dec 2012 ?? ?Print Version ?Bookmark and Share

Keywords:SSRW? SuVolta? bulk planar CMOS? deeply depleted channel? PowerShrink?

A third manufacturing option to follow the conventional bulk planar CMOS is being evaluated by chip giant Globalfoundries Inc. The company is evaluating super-steep retrograde well (SSRW) technology which will create a ground plane under a transistor using a doping technique.

The technology appears to be very similar to that developed by SuVolta Inc. although Globalfoundries has declined to say whether it is working with or in negotiations with SuVolta.

If adopted, the SSRW process would likely be in addition to previously announced 14XM 14nm FinFET process due in 2014 and its licensing of 28nm and 20/14nm fully-depeleted silicon on insulator (FD-SOI) manufacturing process technology from STMicroelectronics.

FIG 1

Figure 1: Schematic cross-section of Deeply Depleted Channel PowerShrink transistor technology. (Source: SuVolta).

However, it could potentially compete with both processes for design wins.

The possibility that Globalfoundries could pursue all three options underscores the challenges facing conventional bulk planar CMOS.

Globalfoundries CEO Ajit Manocha referred to SSWR in a presentation during the International Electron Devices Meeting (IEDM) in San Francisco earlier this month. Manocha said SSWR C alongside FinFETs and FDSOI C represents a manufacturing option for fully depleted transistor architectures and that fully depleted transistors offer superior low voltage and electrostatic performance along with scalability. (see Globalfoundries CEO: Time for foundry 2.0)

When SuVolta introduced its deeply depleted channel (DDC) PowerShrink transistor technology it pitched it as an alternative to FinFET and FDSOI processes.


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