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Implementing asynchronous logic in COTS FPGAs

Posted: 14 Jan 2013 ?? ?Print Version ?Bookmark and Share

Keywords:synchronous? asynchronous? logic circuit?

This is an interesting one. However, before we begin, I'd first like to "set the scene," because it may be that some of our younger members aren't 100% aware of what we mean by "synchronous" versus "asynchronous" when it comes to logic circuit design.

The way in which I visualise this is as shown in the diagrams below. Let's start with a synchronous circuit in which we have "chunks" of combinatorial logic separated by blocks of registers. The reason this is referred to as a synchronous circuit is that everything is synchronised to a common clock.

Figure 1: Synchronous circuit.

One big advantage of the synchronous approach is that it's well understood and the vast majority of our design and verification tools are tailored to this way of doing things. The main disadvantage is that we have to design for a worse-case scenario. In its most simplistic form, this means that we calculate the maximum delays (due to worse-case temperature, voltage, and process variables) and then set the maximum clock frequency accordingly. The problem here is that when the device isn't working under worse-case conditions, we end up "leaving performance on the table."

The alternative is to create an asynchronous, or self-timed, circuit as illustrated in the image below. The idea here is that we get rid of all of the registers and there is no clock. Instead, each "chunk" of combinatorial logic uses control signals to communicate ("handshake") with its adjacent counterparts to inform the "upstream" logic when it is ready to accept new data and to inform the "downstream" logic when it has new data to pass on.

Figure 2: Asynchronous circuit.

There are several potential advantages associated with this asynchronous approach, not the least that we no longer have a clock, which can be a routing nightmare and consume an inordinate amount of power in a synchronous implementation. In addition to making things easier to route and consuming less area and power (we no longer have any registers), the asynchronous circuit will always run at its maximum possible speed. Also, if there isn't any data, then the asynchronous circuit will happily sit there waiting, unlike its synchronous counterpart, which (unless we do something about it) will keep on clocking away burning power, even if it's not doing anything useful.

The big downside to asynchronous design is that there are few (if any) design and verification tools targeted at this domain.

And why am I waffling on about this here? Well, I just received a rather interesting email as follows:

Hi Max, this is Javier D. Garcia-Lasheras (or just Javi, it's much more easier!!!). The purpose of this mail is introducing you an open source project that I think you may be interested in. The project is related to the efficient implementation of asynchronous logic circuits over COTS FPGA devices.

In 2001, I started a research in the topic of implementing asynchronous circuits in custom IC designs. The huge costs associated to ASIC design forced me to start prototyping the systems over commercial available FPGAs... and this issue showed to be a great deal !!.

The designed FF + LUT-based asynchronous circuitry (strongly inspired by Ivan Sutherland's micro-pipeline concept) performed so good in terms of speed, power consumption, EMI & logic efficiency, that soon after (Q4 2005) different institutions and venture capital became interested in launching a start-up focused in asynchronous IP-Cores & System Designs for FPGAs: the AsyncArt project.

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