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Accelerate tester-based silicon debug (Part 2)

Posted: 15 Feb 2013 ?? ?Print Version ?Bookmark and Share

Keywords:verification for test stage? debugging? SoC?

Issue Analysis. For example, say the core makes a 4-beat wrapping burst read for every burst operation, with cache enabled with each read of 64 bits. If the start address is not 256bit aligned, we'll again end up in some ECC errors while reading uninitialized memory in the first burst fetch due to the problems discussed in Must-do practice #3.

Solution. The start address must take care of the burst operation of the core and the enablement of its cache and make the start address alignment accordingly.

Must-do practice #5
The porthole base memory location must be initialized through the start-up constrained random testing (CRT) code.

Issue Analysis. We use portholes for information printing in the patterns. Specific system memory locations are to be used for this. This includes an 8bit write in the porthole location. For some core-platform systems, there is always a Read-Modify-Write (RMW) for 8-16 bit writes to System RAM. But since the read part of the RMW is 32bit, we will end up with ECC errors while writing 8bit if we do not initialise these porthole base locations before handing through the start-up CRT code.

Solution. The porthole base memory location must be initialized through the start-up CRT code.ÿGenerally these information prints are only required for debugging and development. As a result,ÿthe testbench must have provision for a switch that can be passed specifically for tester patterns, which will suppress the printouts but still allow use of the macros (such as for register access). This will eliminate the problem altogether.

Must-do practice #6
The linker files used for making the hex code to be loaded and executed should be such that the hex does not have any address holes in it.

Issue Analysis. In case of holes, that portion of the memory would remain uninitialized/unwritten with the result that there is a high probability of code execution jumping to these empty locations and getting accesses (due to burst accesses), thus leading to exceptions and ECC errors.

Solution. Ensure that the testbench infrastructure for tester patterns at simulation level does not leave any holes in the generated hex.

Must-do practice #7
Always use zero-padding or fillers at the end of the hex so that no un-initialized locations are accessed during executions involvingÿlong instruction pipelines, or instruction bus fetch width constraints, or burst accesses.

Issue Analysis.ÿPowerPC cores have long instruction pipelines, so they will prefetch some additional data while fetching one instruction. Also the core instruction bus will always fetch a minimum width read and may have burst accesses enabled. So if the end locations of the hex are not aligned, during fetching of some instructions the core may end up fetching data from uninitialized locations with random ECC values even though it is fetching a valid instruction. This may result in ECC errors which may cause the core to get exception flags and stop executing altogether.

Solution.ÿDuring the linker and make process, care should be taken to put some filler codes at the end of hex in such a way that whatever code it puts in memory will be aligned so that un-initialized memory location accesses occur because of the following: long pipelined accesses, burst accesses or minimum width of bus instruction fetches. This can be done by using scripts to do a zero-padding at the end of the hex.

Must-do practice #8
While doing Resim (resimulation), loadings should be kept to a minimum in the VFT environment. This can be done through the use of earlier functional gate level simulations (GLS) replicated in the resim testbench.

Issue Analysis. In the case of some analogue models and memories, some of these behaviour need to be forced in the functional testbench, for example forcing x-generation logic, initialisation of portholes memories, or programming test rows of flash. Currently in the resim environment the functional testbench isn't ported as is. But the same design is used to create the VCD, so X-corruption can occur there too.

Solution.ÿBefore starting Resim, such things should be replicated for Resim from VFT environment. Also, all necessary forcing or loading needs to be replicated from functional testbench to the resim environment.

Must-do practice #9
Care must be taken to ensure that no valid pad can be designated x/z for any portion of the VCD for the tester pattern. Also all unused pads must be masked off in the VCD.

Issue Analysis. For patterns with analogue behaviours and analogue pads being tested, the unused pads should be masked in the resimulation environment. If they are not, they get looped back and thus a high-z state occurs on these pads for some time duration due to delay in do-> pad path. This leads to x corruption in design.

Also all valid pads being probed or driven in the VCD must never be allowed to be x/z for any portion of time in the VCD since that again can cause the same issue as above.

Solution. Automatic script analysis must be enabled to find out all pads with x/z state, and either mask them off if they are unused or drive them with safe value when not driven actively.

Other important VFT practices
Some other practices that ensure smooth porting and direct mapping of the simulation behaviour of the VCD/patterns with the behaviour observed on tester include:

Provide the maximum possible time for analogue modules to get stable and provide their status (for example, the status from the voltage regulator for Power-on-reset de-assertion) and also for the maximum possible scanning time for initialisation data from on-chip flash, etc., at start-up should be considered. Accordingly, you should delay programming in the VCD, no matter what time factor is visible during simulation due to usage of behavioural models.

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