Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Memory/Storage
?
?
Memory/Storage??

Memory test tip: Boost flash memory testing

Posted: 25 Feb 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Source measurement unit? non-volatile memory? NAND?

Source measurement units (SMUs) are the most frequently utilised instruments in parametric test systems because they can supply DC voltage or current to the device under test (DUT) and simultaneously measure the resultant voltage or current. For some device testing, however, particularly in the case of flash memory, voltage must be applied in a time-controlled manneroften on the order of just a few microsecondsto prevent the DUT from overheating or overstress. As enterprise SSDs represent an increasingly large portion of the flash memory market, accurate lifetime evaluation of components and modules becomes more important than ever. Given that SMUs are not designed to modulate output voltages at the nanosecond scale, a pulse generator is typically a better choice. Let's take a closer look at ways to optimise flash memory test for the most reliable results.

Flash memory basics
The dominant form of solid-state, non-volatile memory technology is currently flash memory. It is used in a wide variety of devices and applications, ranging from the common USB "thumb drive" to smartphones, MP3 players, and digital cameras. Flash memory is part of a class of MOS devices that use floating gates. There are two types of flash cells: NOR and NAND. In NOR technology, the storage cells can be programmed and erased individually. Unfortunately, the storage densities for this type of flash memory are comparatively low. With NAND devices, it's possible to write to the cells individually, but they must be erased in blocks. NAND-type memory has a much higher storage density and is by far the most dominant of the two types.

In addition to the floating gate, NAND flash memory cells usually have a control gate, drain, source, and bulk (figure 1). Both during endurance testing and in actual use, a memory cell is repeatedly set (programmed) and reset (erased) by applying or removing charge from the floating gate. Charge can be applied or removed from the floating gate of any type of flash memory cell via Fowler-Nordheim (FN) current tunnelling or via hot-carrier injection (HCI). In a normal CMOS transistor, both of these mechanisms cause device degradation and are usually to be avoided, but in the case of flash memory, they are essential to the function of the device. At the same time, FN tunnelling and HCI are also the reason flash memory cells have a limited lifetime.

Figure 1: NAND flash memory cells have a source and drain handled by a control gate (centre). Applying charge to the floating gate sets (programs) the cell and removing charge resets (erases) it.

When charge is applied to or removed from the floating gate, the threshold voltage (VT) of the underlying transistor changes (figure 2). This threshold voltage change is what allows the flash memory cell to be used as a memory storage device. Further, once the charge is injected into or removed from the floating gate, the floating gate remains in that state even after power is removed, which means flash memory is non-volatile.

Figure 2: Charge transfer in a NAND flash cell controls the set (left) and reset (right) process.


1???2???3?Next Page?Last Page



Article Comments - Memory test tip: Boost flash memory ...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top