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Impact of the Cloud on FPGA design

Posted: 06 Mar 2013 ?? ?Print Version ?Bookmark and Share

Keywords:cloud computing? FPGA? Place-and-Route?

From online payments and electronic banking transactions to organising company documents and mission-critical supply chain management systems, cloud computing now has an ever-present role in both consumer and enterprise applications. In general, cloud computing's "pay-as-you-go" elasticityrequiring little upfront investmenttends to be its main value proposition to IT departments, although security and service disruptions are potential risks that come to mind.

But what does cloud computing mean for the FPGA design engineer? How can seemingly unlimited server resources help engineers in our daily work? This article examines the benefits and potential pitfalls of cloud computing in FPGA design from a practical, day-to-day viewpoint.

A typical workflow for an FPGA designer working on a design looks like this:

???Design Entry
???Place-and-Route (P&R)
???Timing analysis, design rule checks
???Testing in hardware
Note that I am purposely omitting steps such as software development and debugging, system integration of separately-implemented blocks, etc. in order to reserve rich fodder for future discussions.

Out of the steps above, Synthesis and P&R are steps that I consider to be the most...

Iterative: After each synthesis and P&R build, results are analysed, design changes are made, and run again.

Compute resource-intensive (in terms of CPU cores and memory): Depending on the design, the FPGA software tools can compile faster or slower with multiple cores and more memory, but in general, having more RAM seems more important than having more cores.

Time-consuming: A heavily-utilised design with aggressive constraints can easily take a few hours or even a day to route successfully.

Talking with other designers, the above observations seem true whether or not their FPGA designs are used for ASIC prototyping efforts or are shipped with the final product.

From an IT resource point of view, the immediate benefits of cloud computing are clear. If FPGA software tools are available on a cloud-like infrastructure along with a sufficiently large pool of tool licens ('licence' when noun)es, I (or any designer for that matter) can fire off synthesis and P&R tasks in parallel almost at will. There will be few concerns about insufficient servers or licens ('licence' when noun)es to run those builds, or if the builds are hogging company servers and preventing colleagues from running their tasks. Typically, things start to get hairy during integration time or near deadlines. During peak periods when everyone is trying to tape-out or close timing, the ability of a cloud to handle the peaks and troughs of compute resource demand makes much sense. Correspondingly, with a cloud-like resource to call upon, a CAD/IT department will probably have less trouble forecasting server requirements and planning budgets for upcoming quarters. Concerns about IT over-investment and under-investment are alleviated.

However, getting more compilation resources and reaping IT benefits is arguably just the tip of the iceberg. How can cloud computing really help an FPGA engineer complete a design in less time than before?

"So what if I can run a hundred different synthesis and place-and-route builds at the same time? There has to be smart way to quickly analyse the results of those hundred iterations, so I can compare their differences and get an idea of what steps to take next. Is this going to require changes to my RTL? Can a constraint change potentially eliminate timing errors?"

These are questions that can be addressed by carefully tweaking and re-running the design. The question is, can running more builds in the same amount of time result in better answers?

From a workflow and design methodology perspective, it makes sense that, given the ability to run multiple builds at the same time, suddenly a lot more data could be obtained for comparison and analysis. This data, mostly in the form of timing and utilisation reports, can be examined in bulk to decide the next steps. When a design fails to meet timing, instead of re-running one or two builds with different tweaks and subsequently poring over the reports, now timing results can be analysed from a lot more builds done in parallel.

The figure shows timing slack values (Y-axis) plotted against 30 different synthesis and P&R builds (X-axis) for an actual design that I ran using a compute cloud.

Figure: Timing slack values (Y-axis) plotted against 30 different synthesis and P&R builds (X-axis) for an actual design that I ran using a compute cloud.

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