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Performing synthesis-aware clock analysis

Posted: 23 May 2013 ?? ?Print Version ?Bookmark and Share

Keywords:clock tree synthesis? signal integrity? PLL?

The intention of a clock tree synthesis (CTS) tool is to create a balanced clock network with short insertion delay, smaller skews, and as few buffers as possible. Long clock insertion delays will create large on-chip variation (OCV) on clock network, which makes timing closure harder to accomplish. Large clock skews will add to the timing closure problem.

Clocks are fast-switching signals by design. In today's SOC designs, the number and complexity of clock networks require a large number of buffers to sufficiently drive the clock signals around the chip, thereby increasing power consumption. This increase in power consumption is a major problem in wireless and handheld device markets, which are primarily driving today's semiconductor market.

Modern SOC designs use complex clock structures, and the number of clock trees is growing from a handful to a few hundred. Prior to the availability of CTS, physical designers did not have adequate tools to analyse clock structures. Since CTS tools are not logically aware, clock constraints are used to optimise the clock graph that CTS will work on.

However, the number of clocks in today's designs has exploded the complexity of clock constraint generation, which for the most part is a manual task. This often results in the generation of improper or non-optimal clock constraints, leading to post-CTS clock structures with long clock latency, large clock skew, and high buffer count.

In addition, modern SOC designs use advanced techniques such as multi-voltage domains to reduce chip power, and such structures make the balancing of clock networks very difficult.

Today's complex clock structures
The clock network used to be a simple structure, where one clock root drove a list of flip-flops; hence, it led to the term clock tree. However, in today's complex SOC designs, the clock network is often made up of hundreds of primary clocks and several times more generated clocks. It is no longer a clock tree but rather a clock graph. These designs are not only populated with generated clocks using clock dividers, but they often overlap with each other too. Also, clock gating cells are used to reduce dynamic clock power. All these clock components make the implementation of clock graph a very complex task.

Modern designs use several design modes, each of which may include several functional and test modes. Different modes typically have different clock definitions and thus different clock networks. Balancing a clock network in one mode will not necessarily balance the clock in the other mode, which is a challenge.

Further, today's SOC designs include some design IPs where clock networks have been predesigned and are typically un-touchable. Those fixed clock structures additionally complicate the balancing of clock networks.

Figure 1: Communication gap of front-end and back-end teams.

Gap between frond-end and back-end teams
A clock network is always designed by a front-end design team and implemented by a back-end implementation team, and implementation is done using CTS tools. In reality, the front-end team cannot anticipate the physical constraints imposed by implementation tools and hence are unable to define constraints that are implementation aware. With timing and power being orthogonal to each other, the back-end team is unable to fully replicate what the front-end team wanted with the fewest number of buffers. This is a major gap in the clock design-to-implementation process. Both teams end up seeing two different views of the clock network. In theory, the clock network seen by a back-end team should be identical, or at least a superset of, the clock network seen by the corresponding front-end team. When it is a superset, the clock network should be optimised to look as close as possible to the clock network as seen by the front-end team.

Figure 2: Design netlist, SDC files, and clock specifications determine clock networks.


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