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Memory/Storage??

Addressing memory scaling concerns

Posted: 08 Jul 2013 ?? ?Print Version ?Bookmark and Share

Keywords:DRAM? NAND flash memory? memory scaling? PCM? STT-MRAM?

We are currently investigating another increasingly significant obstacle to MLC NAND flash scaling, which is the increasing cell-to-cell program interference due to increasing parasitic capacitances between the cells' floating gates. Accurate characterisation and modelling of this phenomenon are needed to find effective techniques to combat program interference. In recent work, we leverage the read retry mechanism found in some flash designs to obtain measured threshold voltage distributions from state-of-the-art 2Y-nm (i.e., 24-20 nm) MLC NAND flash chips. These results are then used to characterise the cell-to-cell program interference under various programming conditions. We show that program interference can be accurately modelled as additive noise following Gaussian-mixture distributions, which can be predicted with 96.8% accuracy using linear regression models. We use these models to develop and evaluate a read reference voltage prediction technique that reduces the raw flash bit error rate by 64% and increases the flash lifetime by 30%.

Conclusion
We have described several research directions and ideas to enhance memory scaling via system and architecture-level approaches, by co-designing memory and other system components as well as with cooperation across multiple levels of the computing stack, including software, microarchitecture, and devices. We believe such approaches will become increasingly important and effective as the underlying memory technology nears its scaling limits at the physical level.

Acknowledgments
I would like to thank my PhD students Rachata Ausavarungnirun and Lavanya Subramanian for logistic help in preparing this manuscript. Many thanks to all my students in the SAFARI research group and collaborators at Carnegie Mellon as well as other universities, whom all contributed to the works outlined in this paper. Thanks also to our group's industrial sponsors over the past few years, including AMD, HP Labs, IBM, Intel, Nvidia, Oracle, Qualcomm, Samsung. Some of the research reported here was also partially supported by GSRC, Intel URO Memory Hierarchy Program, Intel Science and Technology Centre on Cloud Computing, NIH, NSF, and SRC.

Part of the structure of this paper is based on talks I have delivered at various venues on Scaling the Memory System in the Many-Core Era between 2010-2013, including at the 2011 International Symposium on Memory Management and ACM SIGPLAN Workshop on Memory System Performance and Correctness [54]. Section VII of this article is a much condensed and slightly revised version of the introduction of an invited article that is to appear in a special issue of the Intel Technology Journal, titled "Error Analysis and Retention-Aware Error Management for NAND Flash Memory" [7].

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About the author
Onur Mutlu is the Strecker Early Career Professor at Carnegie Mellon University. His research is in computer architecture, especially memory system design and management. He was a recipient of the IEEE Computer Society Young Computer Architect Award, Intel Early Career Faculty Award, and a number of best paper awards.

Note: This work was first presented at the 2013 International Memory Workshop and appears here courtesy of the IEEE.

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