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Altera demos Interlaken IP core on OCTEON processors

Posted: 01 Aug 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Altera? IP core? OCTEON? processors? FPGA?

Altera recently announced the interoperability of its Interlaken intellectual property (IP) core on Stratix V FPGAs with Cavium's OCTEON multi-core processors. This accomplishment simplifies an OEM's device decision-making process by ensuring chip-to-chip connectivity upfront.

"Altera's flexible Interlaken IP enabled us to quickly show interoperability between our products," said John Bromhead, director, Solutions and Services at Cavium. "This solution gives our customers the added assurance that when they develop with Altera FPGAs and Cavium's OCTEON processors, the devices will work seamlessly together. The ease of interoperability also helps customers meet tight time-to-market windows."

The Altera Interlaken IP core is ideal for multi-terabit routers and switches for access, carrier Ethernet and data centre applications that demand IP configurability to optimise for various traffic profiles, and scalability for next-generation platforms. The Interlaken IP includes Altera's technology-leading transceivers (PMA), PCS, and MAC layers. The PCS layer is hardened within the Stratix V and Arria V FPGAs, thereby saving customers 30 to 50 per cent on FPGA logic resources. In addition to resource savings, the Interlaken IP has been through extensive simulation verification and has been proven to work on internal and customer platforms.

The Altera Interlaken IP core provides high throughput and performance when workloads are at their peak. It features more than 20 parameters and settings provide the needed flexibility for system performance tuning, scalability and interoperability. The core also boast data rate and lane support up to 12.5G and x24 lanes while offering standard and customised Interlaken IP cores. It is also compliant with Interlaken Protocol Definition v1.2.

Further information regarding the Interlaken IP core can be found here.





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