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Design Linux-based femtocell base-station (Part 1)

Posted: 25 Sep 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Femtocells? small cells? IP? software performance engineering? Linux?

Femtocells/small cells are considered to be the key to next-generation wireless operator networks due to the coverage, capacity and cost advantages they provide compared with large cell deployments. Using existing IP backhaul infrastructure (e.g. DSL/FTTH) and self-organising networks (SON), deployment is simple and low-cost.

However, in order to achieve the system price point associated with wide consumer deployment, system cost needs to be orders of magnitude below that of a traditional macro cell solution. Also, power supply restrictions leave little room for 'over-design' on either the hardware or software side.

This two-part article describes one way to achieve this goal. In this first part we describe an efficient low-cost femtocell design in which a Linux-based fast-path software architecture is implemented on base-station-on-a-chip hardware containing all the necessary digital processing, from Ethernet interfacing all the way to A/D converter, including the control plane, packet processing, and Layer-1 signal processing (figure 1).

In Part 2, we will describe how to use the principles of software performance engineering to integrate hardware and software elements and to evaluate whether or not the resulting implementation meets the design goals.

Figure 1: Base station on a chip.

The particular base-station-on-a-chip hardware chosen is based on Freescale's BSC913x family (figure 2), which targets a variety of use cases, for example 100Mbps DL, 50Mbps UL operation with 16 active UE operation. On the Layer-1 side, such performance is achieved by using a mix of a StarCore SC3850 high-performance DSP core and the MAPLE hardware acceleration for a.o. the physical downlink shared channel (PDSCH) and physical uplink processing element, which performs decoding of physical uplink shared channel (PUSCH) resulting in decoded information bits.

The remainder software stack (L2, L3, OAM, transport components) runs on the Power Architecture/e500 core with associated hardware acceleration for IPSec, 3GPP ciphering, timing, etc.

Figure 2: BSC9130/1 Base station on a chip.

Achieving the challenging system throughputs on a single-chip solution leaves little room for inefficiencies on the software architecture and implementation. As such, close cooperation between software and hardware development teams is crucial during architecture and implementation phases. The work presented focuses on the challenges imposed on the GPP Power Architecture e500 processor software architecture and the optimum solution to such challenges as reached by close cooperation between 3rd party software developers and Freescale.

Figure 3: Hard Real-Time Linux approach with Xenomai development framework.

Using Linux as a fast-path OS architecture
In order to achieve portability, debugability, and code re-use targets, Linux is an obvious choice for the OS for the small-cell platform. However, as well known in the industry, Linux is not capable of achieving the 1 mSec hard real-time deadlines required for LTE (long term evolution) applications. Two industry approaches exist to enhance Linux to achieve real-time deadlines:

Real-Time Linux (figure 3) approaches such as Real-Time Linux and the Xenomai development framework. Such approaches create an isolated real-time environment in parallel to Linux by trapping interrupts. This means that applications need to be ported to the thin kernel that is provided by the real-time portion of Linux. Besides this drawback, debugability can be an issue (the standard user space Linux toolset is not available).

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