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Xilinx, ADI achieve JEDEC JESD204B interoperability

Posted: 26 Sep 2013 ?? ?Print Version ?Bookmark and Share

Keywords:JEDEC? JESD204B? data converter?

Xilinx Inc. and Analog Devices Inc. have announced that they have achieved JESD204B interoperability between Xilinx JESD204 LogiCORE IP in the Kintex-7 FPGA and the ADI AD9250 analogue-to-digital high-speed data converter. According to the firm, this achievement is a significant milestone in promoting the widespread adoption of this new technology.

Transition to the high-speed transceiver based JESD204B standard opens up significant upsides for improving system performance in communications equipment. JESD204B offers manufacturers numerous advantages, including higher level system integration, deterministic latency capability, easier multi-channel synchronisation, smaller and lower-cost device packages, reduced PCB complexity and cost, and better system modularisation.

"By demonstrating JESD204B interoperability, Xilinx and ADI have shown leadership in this important new standard," said Harpinder Matharu, senior product manager, Xilinx communications business unit. "Working together, Xilinx and ADI can enable manufacturers to take advantage of JESD204B to accelerate time-to-market for their new products by shortening development time, reducing system test effort and minimising development issues."

"Interoperability testing between Xilinx FPGAs and ADI data converters is a significant milestone for analogue and digital designers worldwide and it will reinforce industry confidence in this emerging high-speed converter interface. The results confirm that off-the-shelf ADI JESD204B data converters and Xilinx FPGAs work together seamlessly," said Dave Babicz, director, Global Alliances, Analog Devices. "ADI's portfolio includes the clocks, amplifiers and the other components, tools and software needed to successfully implement a JESD204B-based data converter-to-FPGA design, and together, ADI and Xilinx provide a complete and verified solution."

Developed by the JEDEC standards organisation, the latest JESD204B specification overcomes connectivity limitations between the logic device and the multiple data converter devices used in multi-mode wireless radios, wideband backhaul modems, ultrasound monitors and other high performance equipment. JESD204B eliminates the connectivity bottleneck, complexity and improves system performance while lowering cost.

The joint interoperability lab testing successfully validated JESD204B subclass 0 and subclass 1 (deterministic latency) functionality by running a comprehensive set of tests between the Xilinx Kintex-7 XC7K325T FPGA and ADI's AD9250 device.

Xilinx JESD204 LogiCORE IP is boasted by the firm as the industry's first JESD204B soft IP that supports continuous line rates from 1-12.5Gb/s on 1, 2, 3, 4, 5, 6, 7 or 8 lanes using GTX or GTH transceivers in Zynq-7000, Kintex-7 and Virtex-7 28nm devices and GTP transceivers in the 28nm Artix-7 FPGA family. Xilinx JESD204B IP can be configured as a transmitter or receiver and supports transceiver sharing between a transmitter and receiver link.

Xilinx JESD204 IP is available for free evaluation at http://www.xilinx.com/products/intellectual-property/EF-DI-JESD204.htm.





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