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ADC in SoC: Mere placeholder or vital subsection?

Posted: 04 Dec 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Analogue-to-digital converters? ADCs? SoC? CPU? PGA?

Analogue-to-digital converters (ADCs) are found in almost all embedded applications. This fact has lead manufacturers of microcontrollers and System on Chip (SoC) architectures to integrate one or more ADCs into their product offerings. In many applications, these integrated ADCs are good enough to replace a dedicated ADC used in the application. Careful selection of an SoC that has an ADC with specifications closely matching the application yields a compact system at a lower cost.

There are many specifications to be taken into consideration while selecting an ADCresolution, sample rate, noise performance, and power consumption, to name a few. However, in controllers that integrate an ADC, there are other specifications that are worth checking as well. These include CPU overhead, the option to multiplex multiple signals, and flexibility in pin assignment. Thus, evaluating an integrated ADC in an SoC can be a little bit trickier than evaluating an external ADC.

Why a device with integrated ADC?
Compact system: An integrated ADC helps in reducing the board size and BOM (Bill-of-material). Based on my experience, most system designers aim to reduce the PCB size. Some SoCs also have integrated op-amps or programmable gain amplifiers (PGA) that further reduce component count on the PCB (figure 1). An SoC that offers flexibility in assigning various pins for analogue functionality can help reduce layout complexity as well.

Figure 1: An MCU with an integrated ADC like the PSoC 4 from Cypress can help reduce board size and system cost as can integration of op-amps and programmable gain amplifiers (PGA). SoCs that offer flexibility in assigning various pins for analogue functionality can reduce layout complexity as well.

Lower Power consumption: Most SoCs provide an option to power down various blocks when not in use. For battery-powered applications or other power critical applications, this means integrated ADCs can help reduce average power consumption by being able to power down the ADC when it is not needed. There are various applications where analogue-to-digital conversion is not needed all the time. For example, a weather monitoring system needs to measure a physical quantity just once a minute and report to a host system. In this application, the controller can take a sample, power down the ADC, transmit the result to the host system, and then go to sleep. Some devices support various power modes that automatically disable all the resources when entering a low-power mode and then power them up when device enters into a higher-power mode. This helps reduce firmware overhead as well speeds implementation.

Lower system cost: Generally, the cost of a MCU+ADC is more compared to a device with an integrated ADC with similar specifications.

There may be other issues worth considering while selecting a device. As integrated ADCs bring analogue and digital counterparts of the system together on same silicon, this may introduce noise from the digital sub-system into the analogue sub-system. Be sure to check noise specifications carefully. Some manufacturers place a proper guard band around the analogue section of chip to keep noise to a minimum. Also, noise may vary based on what other resources are being used on the chip. Thus, noise performance analysis should be performed when all required resources are active on the chip.

Another challenge can be routing of traces carrying analogue resources. No doubt, a device that supports analogue functionality on all pins makes it is easier to pick a pin based on the placement of the sensor or the signal source. However, most SoCs limit analogue functionality to a select subset of pins. Limiting routing options in this way may force analogue traces to travel alongside traces carrying digital signals, which may add significant noise to the signal. This issue can be solved by some PCB layout best practices like keeping the analogue and digital lines isolated as far as possible, surrounding analogue signals with GND plane, among others, to reduce the capacitive coupling between analogue and digital traces.

Sometimes assigning a digital pin next to an analogue pin can also degrade the overall noise performance due to pin-to-pin leakage. If possible, leaving a pin unused between analogue and digital pins can help in improving the performance.

Usability check of ADC while selecting a SoC
Some specifications are common across all ADCs, whether they are integrated or discrete C resolution, sample rate, input range, etc. As these are generic specifications, we will not talk about them in this article. We will instead focus on those that relate specifically to integrated ADCs.

CPU overhead: In some SoCs, CPU bandwidth is required for analogue-to-digital conversion. Generally, the number of CPU cycles required for each sample is mentioned in the ADC specifications. From a system integration and performance point of view, it should be calculated if these many cycles can be spared for analogue-to-digital conversion. Some SoCs use interrupts for conversion which, for some applications, can introduce significant overhead and interrupt latency, potentially causing erroneous conversion results. Before selecting an SoC, the effect of CPU bandwidth taken by the ADC should be carefully studied to make sure that sufficient CPU bandwidth is available for the main application when the ADC is active.

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