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Overcome challenges in FPGA-based prototyping

Posted: 14 Apr 2014 ?? ?Print Version ?Bookmark and Share

Keywords:system-on-chip? FPGA? prototype? RTL? debugging?

With RTL partitioning, it is possible to skip repartitioning if incremental changes to the source code do not affect partitioning results. We distinguish two scenarios. In the first case, changes are local and do not cross partition boundaries (e.g., module M1). The initial solution remains 100% valid. To obtain an updated design implementation on the board, one needs only to rerun synthesis-place-and-route for the relevant FPGA. In the second case, changes crossing a partition boundary induce partitioning updates (e.g., modules M2 and M3). This can be performed incrementally by re-injecting the original assignments as input constraints. This could allow for preserving much of the original solution and would allow the partitioner to find incremental assignments to complete the new solution.

With gate-level partitioning, when major RTL changes occur, it is mandatory to rerun the overall design synthesis and overall partitioning. Incremental and modular synthesis can be used to handle local RTL changes and shorten run times.

Full system verification and simulation
Board bringup can be painful and time-consuming. Once a design is implemented in FPGA hardware, the system becomes difficult to debug. A full system simulation helps ensure that no logic errors are present. When this is combined with systemwide STA, the system is proven error-free, and bringup is straightforward.

It is very helpful that the partitioned design can be simulated at the RTL level before going to time-consuming implementation tasks (probing and debugging IP insertion, synthesis, and FPGA P&R). Allowing verification at each step of the prototyping flow is one of the main advantages of RTL partitioning.

Running simulation on synthesised netlists at the gate level is time-consuming and inconvenient due to logic pruning, name changes, and initial RTL hierarchy modifications. The debugging task becomes very painful on such designer-unfriendly netlists.

Bug-hunting methodologies and tools
The retention of RTL-level information allows designers to implement capture probes and triggers quickly using RTL-level signal names. Such visibility can be added in the RTL before or after partitioning. Depending on one's bug-hunting methodology, debugging resources may be limited in the FPGAs, and the number of signals one can probe may be constrained.

As shown in figure 13, probe insertion may be performed before or after RTL partitioning. Inserting probes after partitioning gives designers more flexibility to take into account available debugging resources in each FPGA.

Post-synthesis signal probing leads to false positive due to advanced synthesis optimisations (such as inverter push-through). Consequently, adding probes after gate-level partitioning is inconvenient. With a gate-level methodology, observability points must be inserted in the initial RTL before synthesis and partitioning. This may create additional complex constraints to the partitioning process due to the limited debugging resources available in each FPGA.

Figure 13: RTL debug instrumentation can be performed before or after partitioning./i>

Timing-driven hybrid partitioning
Taking all the preceding discussions and considerations into account, we at Flexras set about addressing the need for efficient FPGA partitioning tools to achieve error-free and predictable time to prototype. The goal was to tackle the partitioning problem in an innovative way that would unify the advantages of accurate area/timing estimation at the gate level and partition generation at the RTL level. This goal has been accomplished with the release of our Wasga Compiler. The main concept behind hybrid partitioning is to use accurate gate-level netlists to solve the partitioning problem while implementing the solution on the original RTL design.

Figure 14: Wasga compiler timing-driven hybrid RTL/gate-level partitioning flow./i>

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