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Altera adopts fine-pitch copper packaging for Arria FPGAs

Posted: 22 Apr 2014 ?? ?Print Version ?Bookmark and Share

Keywords:Altera? TMSC? fine-pitch copper packaging?

Altera Corporation and TSMC have teamed up to deploy advanced packaging technology for Arria 10 FPGAs and SoCs.

Altera is the first to adopt TMSC?s patented fine-pitch copper bump-based packaging in commercial production to deliver improved quality, reliability and performance to its 20nm device family.

TSMC's flip chip ball grid array package technology utilises fine-pitch copper bumps measuring less than 150?m. The technology accommodates very high bump counts as required by FPGA products. It also provides excellent bump joint fatigue life, improved performance in electro-migration current and low stress on the ELK (Extra Low-K) layers--critical features for products employing advanced silicon technologies.

The copper bump-based package technology is scalable and ideal for products that feature large die size and small bump pitch. It includes a DFM/DFR implementation from adjusts package design and structure for wider assembly process windows and higher reliability. The technology has demonstrated better than 99.8 per cent production-level assembly yields.

"Leveraging this technology is a great complement to Arria 10 FPGAs and SoCs and helps us address the packaging challenges at the 20nm node," said Bill Mazotti, vice president of worldwide operations and engineering at Altera.

Altera is shipping Arria 10 FPGAs based on TSMC 20SoC process technology and featuring the packaging technology. The chips provide what the company claims is FPGA industry's highest density in a single monolithic die and up to 40 per cent lower power than the previous 28nm Arria family.





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