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DTS-HD decoder minimises processor bandwidth requirements

Posted: 09 May 2014 ?? ?Print Version ?Bookmark and Share

Keywords:DTS? audio decoder? Synopsys? ARC? DTS 5.1?

Synopsys, Inc. has released an audio decoder that minimises processor bandwidth and memory size requirements on the company's ARC single- and dual-core audio processors.

The DTS-HD audio decoder supports all DTS 5.1 channel audio formats. It has earned a certification that ensures compliance with all DTS audio standards, enabling SoC designers to implement high-quality audio playback in a wide variety of consumer electronics including digital TVs, set-top boxes and personal media players.

The decoder features sampling frequencies of 44.1kHz, 48kHz and 96kHz, as well as an ability to decode multiple audio streams. This helps minimise bandwidth requirements of ARC audio processors, enabling them to perform more functions at the same frequency, or run at a lower frequency to reduce power.

It is tolerant of high memory latency, with a processor load of only 52MHz with 100 cycles latency. This is expected to allow easier system configuration for multimedia applications and enable designers to implement their system with slower, lower-cost memory.





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