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Effects of copper stress on smart power technology

Posted: 09 Oct 2014 ?? ?Print Version ?Bookmark and Share

Keywords:SPT7? smart power? over-voltage? recrystallisation? copper?

The hypothesis is over-voltage yield loss is caused by inconsistent offset of threshold voltage or saturation current in matching pair's transistors. Offset brought about by asymmetric power copper coverage induced asymmetric stress on matching pair's transistors. A test chip was then designed to study the effect power copper coverage on over-voltage critical matching pair transistors as shown in figure 4. C11 original layout X15 partial power copper coverage of main bias is on right side, while X16 partial power copper coverage of main bias is on left side. The results are shown in figure 5. Right vs left power copper on main bias show there is the highest delta of 35mV in over-voltage tested at 150C due to asymmetry of power copper coverage. The split of 400C has a wide spread for over-voltage parameters for all designs as the stress is not saturated.

Figure 5: C11, X15 vs X16 designs with 3 different temp on over-voltage measurement.X15 vs X15 had the largest delta on over-voltage due to asymmetry of power copper on critical circuits.

Figure 6: Overvoltage measurement shows higher failure on 400C temp compared to 440 and 460C as insufficient stress on 400C induced larger mismatch.

In summary, the higher annealing temperature has a higher tensile stress on copper. When the stress reaches maximum level which is anneal at 440C, it would cause constant mismatch in the matching pairs transistors, hence lower failure rate on over-voltage parameters. Symmetry design is thus desirable for critical transistors matching in circuits such as current mirrors.

References
[1] J.F.Creemer,P.J. French, "A new model of the effect of mechanical stress on the saturation of bipolar transistors",Sensors and Actuators 97-98 (2002) 289-295.
[2] Tan Chan Lik; Tan Chun Keat ; Thilaga, G. ;Cheng Chin Siong, "A new method on Cu stress measurement by bandgap voltage reference circuit", Electron Devices and Solid-State Circuits 2013 (EDSSC 2013), page 1-2, Hong Kong, Jun 2013.

About the author
Tan Chan Lik is process integration engineer with the Technology Department of Infineon Technologies (Kulim) Sdn Bhd, Malaysia.

Govindasamy Thilaga is product and test engineer with the Technology Department of Infineon Technologies (Kulim) Sdn Bhd, Malaysia.

Tan Chun Keat is process integration engineer with the Technology Department of Infineon Technologies (Kulim) Sdn Bhd, Malaysia.

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