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Determine acceptable jitter level in embedded design

Posted: 12 Nov 2014 ?? ?Print Version ?Bookmark and Share

Keywords:clock jitter? FPGA? microprocessor? C2C? EMI?

For the example PN Plot shown in figure 5, this particular board design has significant spurious content measured at the PLL output. Unfortunately, the spurs are within the integration range of interest for this application, namely 12kHz to 20MHz. As a result, the reference clock's total phase jitter is outside the SerDes chip vendor's specification and a high BER was a result. Root cause analysis, making use of an EMI sniffer, allowed this spurious content to be traced to the synchronous buck-switching regulator used to power the PLL. Layout modifications and passive component changes were implemented to alleviate the problem.

However, some of the spurious content comes from the PLL clock device itself. It's important to keep in mind that any clock synthesiser device can create an array of unwanted sum and difference frequencies. These may be enough in power magnitude to show up as significant spurs on a PN plot.

Today's elegant PLL designs employ advanced silicon design techniques. These advances help to minimise intrinsically generated random and deterministic (spurious) jitter. But for jitter-critical board clocks, it's incumbent on the designer to verify with timing device vendors that corresponding phase jitter specifications for a given clock device are based on PN plots with spurs turned-on.

A flow chart to get you on the right track
The flow chart in figure 6 is intended to guide the board designer to the right jitter specification for his application, and thus the selection of the right clock chip(s).

Figure 6: A flow chart helps to specify the right jitter for your application.

First, determine the application type. Is it a synchronous interface or synchronous logic design, a microprocessor reference clock specification or spread spectrum clock, a high-speed serial communication or SerDes design? In many board designs, often all of these application types need to be addressed, and all have different jitter requirements.

For a synchronous interface or synchronous logic design, you should be dealing with period jitter. Are you working from a P2P period jitter specification? If so, then you need to be certain of two key qualifiers: First, the P2P period jitter you're using from the chip is based on a 10K sample size, per JEDEC (Joint Electronic Device Engineering Council). Second, the chip vendor provides you the assumed BER for their specification. With those two qualifiers, you can arrive at a corresponding RMS period jitter specification for selecting an appropriate clock device.

If it's a consumer electronics application implementing spread spectrum, then you probably should be using a C2C jitter specification. The assumption is that C2C jitter is measured across 1,000 consecutive cycles per the JEDEC Standard. You need to confirm, and if that is the case, then you have a valid C2C jitter specification to qualify the corresponding clock chips.

If it's a high-speed serial communication design, then you should first ask if the serial standard makes use of the traditional spread spectrum analyser methodology for quantifying phase noise. Also, it is important to note exactly what the PHY vendors provide for a specification. Is it P2P total jitter UI, or P2P random jitter UI?

Keep in mind that RMS is only specific to random jitter, where one needs to divide the random jitter requirement by the BER multiplier to knock that down to the corresponding RMS random jitter UI. For random jitter, you can use a PN plot with spurs turned off and then integrate to arrive at an RMS phase jitter value. But, when we take a PN plot with spurs turned on to capture the deterministic jitter and then integrate per the mask, then the corresponding value is no longer RMS and is instead total phase jitter.

The intent of this flow chart is to walk you through a systematic approach for specifying the right jitter for your application. It is designed to eliminate common board design pitfalls detailed in this article.

A useful clock device specification is one that delineates the different output structures and corresponding jitter capabilities of each. It also provides the specifications for the different jitter types outlined in this article so that the designer can qualify for their given application. As an example, consider the Universal Frequency Translator (UFT) shown in figure 7.

Figure 7: A flow chart helps to specify the right jitter for your application.

This configurable clock device has several advanced features ideally suited for communications line-card applications. It provides an impressive mix of high performance (e.g., low phase noise) and flexibility in one device. To provide this flexibility, the device employs a mix of both integer- and fractional-based output dividers, with corresponding RMS phase jitter differences noted for each output type, as shown in this device spec. Also, this device datasheet breaks out PCIe phase jitter performance, per the previously noted PCISIG methodology, in a separate table, thereby recognising the difference in methodology for that serial interface standard.

It's important to recognise that not all use case permutations could ever be captured in a configurable clock datasheet. As a result, the designer is encouraged to request the corresponding jitter performance for their given use case, because results can vary slightly.

About the author
Dean Smith is a Senior Field Applications Engineer at Integrated Device Technology (IDT). Dean received his BSEE from Rochester Institute of Technology.

To download the PDF version of this article, click here.


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