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Reducing SoC power: Where should the focus be?

Posted: 18 Nov 2014 ?? ?Print Version ?Bookmark and Share

Keywords:System-on-Chip? SoC? interconnect? GPU? CPU?

Most efforts to control power consumption in System-on-Chip (SoC) design are focused on the computational units, such as the CPU and GPU. However, other sections of the chip remain largely untapped for energy conservation measures. SoC designers may put themselves at a market disadvantage if they miss the opportunity to reap game-changing power savings from design measures that may cut overall power by as much as 10%.

The SoC interconnect is one area in which efforts to reduce power consumption need be re-evaluated. In computational units such as the GPU or CPU, clock-gating is one of several measures commonly applied to reduce power consumption, but in other areas of the chip, this may have been overlooked.

The big obstacle may be that clock-gating and clock-tree management have become impractical in the interconnect portions of many SoCs because of the growing complexity and feature requirements of advanced designs. However, several SoCs design teams have devised ways to overcome this complexity with a more modular approach to the interconnect fabric, and they are seeing benefits in mobile applications, processors, and set-top box (STB) controllers, where power consumption is a critical.

Let's look at how clock-gating and flop-toggling implemented in the interconnect of a STB controller reduced power consumption over three different operating scenarios: heavy use/worst case, typical, and web browsing.

Video decode activity of a set-top box

Table: Video decode activity of a set-top box chip provides analysis of the effects of clock-tree gating.

This hypothetical design assumes a modular Network-on-Chip interconnect for a midrange set-top box SoC supporting 1080p 120 video display. It uses an interconnect of 11 master and 6 slave Network Interface Units and consumes a logic area 183k gates.

Clock-gated switching activity for the three scenarios offers insight into how this approach works. In the worst-case video processing scenario, the video decoder and the CPU combine to heavily load the system and consume nearly all available DDR memory bandwidth. The second scenario depicts an average case of video decode complexity. The third scenario represents web browsing with no video decode and a modest display rate of 30 frames per second.

Typically, interconnects in STB chips have been implemented with a hybrid system of buses and crossbars. DDR activity on crossbars, for example, has to be enabled for every cycle. A modular interconnect design uses clock-gating to toggle DDR activity to reduce power by a factor of either 2.3x in the first case, 2.5x in the second, or 3.4x in the third.

Experience tells us that toggle savings can be even greater in a standby scenario if a modular interconnect is used instead of a crossbar. Furthermore, larger chips have more master NIU logic that accesses the same limited, shared resources. Such chips have a larger number of flops gated for a larger percentage of time. As a result, toggle savings for a modular Network-on-Chip design improves with increased chip size.

When delving into the relatively unexplored frontier of SoC interconnect power savings, clock-gating and flop-toggling are two important tools if the goal is to reduce overall power consumption. With well-known chip design methodologies, it is possible to gate the clock at each flip-flop during cycles in which toggling is not required. This is applicable to the flops in all interconnect technologies but it does not address clock-tree power consumption.

Building the interconnect from atomic modules of combinatorial logic enables unit-level clock-gating with much finer granularity than is possible within a monolithic crossbar. A modular NoC approach can replace crossbars and buses in many complex SoC designs today and help designers fight the war on power consumption. The key to doing this, of course, is to get designers to shift their focus away from the computational units of the SoC for small periods of time and devote at least some attention to the interconnect. These efforts have reduced power consumption by as much as 0.7-miliwatts. That might seem small, but the market has validated this approach with massive volume production of products using these techniques in the mobile, Digital TV, and STB markets.

About the author
Kurt Shuler is Vice President of Marketing at Arteris and has extensive IP, semiconductor, and software marketing experience in the mobile, consumer, and enterprise segments working for Intel, Texas Instruments, and three start-ups.





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