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Boost data rates with clock generators

Posted: 28 Nov 2014 ?? ?Print Version ?Bookmark and Share

Keywords:data centre? LAN? OTN? Cloud? frequency-flexible clock generator?

To meet the rapidly expanding Internet bandwidth demands of content providers, compute and storage networks for data centres must become flatter and more horizontally interconnected. Known as the "converged data centre," this flatter architecture is required to improve server-to-server and server-to-storage communication within the data centre, which directly impacts latency and the quality of streaming services. In addition to delivering latency performance advantages, the converged data centre architecture is highly scalable and lends itself to software virtualisation of compute server and storage hardware resources, supporting rapid changes in service bandwidth demands. Some vendors refer to this architecture as Software Defined Networking (SDN).

Traditional clock tree designs
As data centre compute and storage networks become horizontally interconnected with multi-gigabit Ethernet, Fibre Channel, and PCIe links embedded into pluggable, high-density blades, they place new demands on system engineers, especially the clock tree designers. Designers must find clock tree solutions that support both increasing functional densities and the multitude of high-bandwidth network protocols while reducing PCB footprints, power and costs.

Let's consider a traditional clock tree design approach for a data centre switch blade, as shown in figure 3. Whether this blade is implemented on a PCB using multiple ICs or based primarily on a single system-on-a-chip (SoC) solution, the compute switch blade's primary function is to support simultaneous, high-bandwidth, low-latency communications between the LAN, compute server blades and storage devices. Data centre switch blades support the consolidation of multi-gigabit LAN and multi-protocol storage traffic into highly scalable networks. However, the traditional clock tree used to support data centre switch blades is complicated (figure 3), requiring eight clock tree components:

???Three crystal oscillators (XOs)
???Three buffer ICs
???Two clock generator ICs.

 Data centre switch blade

Figure 3: Data centre switch blade using traditional clock tree.

Multi-lane SerDes and PHY reference clocks
A major reason for clock tree complexity is that high-speed communications links fundamentally rely on multi-lane, multi-gigabit serialiser/de-serialisers (SerDes) and physical layer devices (PHYs) for each network interface type. SerDes chips and PHYs are critical building blocks for data centre switch blades. Depending on the network type (LAN/ WAN, compute, storage), protocol (GbE, 10 GbE, Fibre Channel, PCIe), and transmission medium (fibre optic cabling, copper cables or PCB backplanes), each multi-gigabit SerDes or PHY device requires a low-jitter reference clock, and many operate at different frequencies. Due to protocol and physical media standard differences, these reference clocks are seldom integer-related.

For example, the 161.1328125MHz clock is fractionally related (by 66/64) to the 156.25MHz clock. This fractional relationship makes the simultaneous generation of low-jitter SerDes clocks much more challenging, as fractional dividers must be used. Fractional dividers used in traditional clock generators produce significantly higher jitter than integer dividers used in integer-only PLL clock generators, forcing designers to use more expensive, dedicated XOs to generate each unique frequency.

CPU, memory and system clocks
While the jitter requirements of some ICs (such as SerDes and PHY clocks) may be very strict, other switch blade functions have less stringent requirements (100MHz PCIe, variable 75 to 150MHz CPU, and 166.66MHz DDR-333 memory clocks). However, given the limited flexibility and integration level of traditional solutions, clock tree designers have been forced to use multiple clock generators and crystal oscillators (XOs) and buffers to complete the clock tree.

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