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ECC bumps up mobile device reliability, efficiency

Posted: 11 Mar 2015 ?? ?Print Version ?Bookmark and Share

Keywords:memory throughput? battery life? JEDEC? LPDDR4? DRAM?

Designers of handsets and tablets face the challenge of increasing memory throughput without compromising battery life as the number of new applications and use cases for mobile devices increases. To help OEMs meet this challenge, JEDEC has defined the fourth-generation Low-Power Double Data Rate (LPDDR4) DRAM standard.

LPDDR4 provides twice the bandwidth of LPDDR3 (table 1). LPDDR4 has also been designed with power neutrality in mind, enabling memory devices based on this technology to provide extra bandwidth while minimising the impact on battery operating life. This makes LPDDR4 ideally suited for a wide range of portable electronics.

Figure 1: Peak Throughput for Mobile Platforms.

LPDDR4 is also being considered for IoT applications, such as wearable electronics, where power is a critical design constraint. The bandwidth and power advantages of LPDDR4 have even attracted the interest of automotive OEMs for use in vehicle sub-systems such as centre consoles.

Single-bit errors
The LPDDR4 specification was designed to accommodate continued advancement in DRAM process technology, which involves shrinking the dimensions of the memory cell. In order to maintain cell capacitance in less area, more complex manufacturing is required. Also, the cell access device weakens, and both bitline and rowline resistance increases, each of which lengthen the time for each memory cell to reach maximum charge. These effects make it increasingly challenging for manufacturers to maintain yields and reliability with subsequent process generations.

DRAM yields are primarily limited by single-bit errors. A few of these errors may be "hard" bits, where a bit is stuck at 1 or 0. These will always be repaired using redundant elements. However, most failing single bits are simply marginal; they work correctly if they are refreshed often enough or written for a longer period of time. The numbers of these bits, while still a very small percentage of the array, do require an increasing amount of redundant elements, which increases die size and complexity. It should also be noted that the DRAM write recovery time (tWR) and 64ms or 32ms refresh specifications are set very conservatively in order to allow most of these weak bits to pass. Without these bits, the refresh and tWR specifications could be relaxed substantially, which would provide performance and power benefits.

Another phenomenon that becomes more prevalent with each process shrink is variable refresh time bits, or VRTs. These are occasional random single bits that change their refresh time after the DRAM is heated (i.e., when the solder reflow is performed for board mounting). While these VRT bits are relatively rare, if they do occur they are troublesome if they occur after the DRAM has passed final test at the manufacturer, which makes repair difficult or impossible.

In an effort to mitigate the costs of post-package repair or scrapped parts, and to maintain acceptable field failure rates, DRAM manufacturers currently test the memory bits at conditions much more stringent than the specification requires. The goal is to find the VRT bits before they actually fail. While this testing is largely successful, the cost is reduced yields. There can be a significant degree of overkill associated with more stringent testing because numerous die that would not actually produce a VRT fail get discarded in the process of identifying actual VRT die. Also, no testing is perfect, and some VRTs may escape and still manage to find their way to OEMs. Given these continuing problems caused by VRT bits, memory manufacturers needed to implement a new technology to increase reliability and control costs for future devices.

Error correcting code
Error correcting code (ECC) is an established memory technology used in a vast array of applications to increase reliability. ECC provides the next level of redundancy for memory ICs by using a Hamming code, which generates a small number of parity bits that are stored in the memory array with the user data. The hamming code enables a short run of bits to protect a much longer data word. For example, Micron's LPDDR4 devices use 8 parity bits to provide correction for a 128bit data word. These parity bits can be used to detect and correct a single-bit error in the 128bit word.

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