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Taking advantage of TSMC's 28HPC process

Posted: 30 Apr 2015 ?? ?Print Version ?Bookmark and Share

Keywords:TSMC? system on chips? SoCs? lithography? EDA tools?

In September 2014, TSMC released its third major 28nm (nm) process into volume production28HPC. Millions of production wafers have come out of TSMC's first two 28-nm processes (the poly SiON 28LP and high-K Metal Gate 28HP/28HPL/28HPM). With 28HPC, TSMC has optimised the process for mobile and consumer devices' need for balance between performance and cost. Using a combination of this process technology and standard cell logic libraries designed specifically for this process, designers can achieve their performance, power and area goals while mitigating schedule risk.

This article describes five areas where designers can take advantage of this new process with the latest logic library technology to optimise the performance, power and area of their system on chips (SoCs). First, designers can improve SoC performance by using the global slow and fast (SSG, FFG) signoff corners enabled by TSMC's tighter process controls with 28HPC. This performance enables the use of lower drive (smaller) logic relaxed cells to close critical timing paths. Second, the 28HPC process reduces area, and therefore cost, as process rules enable library providers to deliver shorter cells with improved routability. Third, these same relaxed rules enable longer channel lengths to be drawn than could be drawn with the 28HPM process to reduce leakage power by up to 50% without use of expensive lithography-based gate biasing. Fourth, TSMC's tighter process controls for the 28HPC process cut power consumption by reducing leakage by 20% in its corner models. Fifth, new logic library features introduced for the 28HPC process, such as multi-delay, multi-setup and multi-bit flip-flops (MBFF), help designers optimise their processor cores for performance and power.

1. Improved SoC performance with global corner signoff
Logic libraries have traditionally been developed with total corner process/voltage/temperature (PVT) simulation corners to reflect the typical P channel and N channel transistor performance, the statistical slowest performance (slow-slow or SS for 3 sigma), and fastest performance (fast-fast, or FF for 3 sigma). These corners are used to simulate typical expected performance, worst case performance (for flip-flop setup) and best case performance (for flip-flop hold) and include the expected die to die, wafer to wafer and lot to lot variability to assure yield.

Because of reduced process variability, TSMC is able to deliver high yielding silicon at a new corner called SSG (for global) which provides a 10 to 15% performance boost over their previous 28HPM process, which required the more conservative SS signoff (figure 1). The process variability improvement can enable processors to run 10 to 15% faster so a 28HPC logic library must be able to support the additional dynamic power and electro-migration requirements for operating circuits at higher speeds.

Figure 1: TSMC 28HPC SSG corner signoff provides a 10 to 15% performance boost over the 28HPM SS corner signoff.

2. Reduced gate leakage with reduced process variability
The HPC process variability improvements reduce transistor leakage so the 28HPC process will show a reduction in leakage of approximately 20% compared to 28HPM based on different process options and conditions (figure 2).

Figure 2: TSMC 28HPC FFG corner signoff shows a reduction in leakage of approximately 20% compared to 28HPM FFG corner signoff.

3. Reduced gate leakage with longer channel lengths
Changes in the TSMC design rules driven by process improvements enable logic libraries to be drawn with multiple gate lengths for a greater range than was possible with the TSMC 28HPM process (figure 3).

At the same time, the new relaxed design rules remove some lithography steps to enable cells drawn with 30 nm, 35 nm, and 40 nm to expand the performance/leakage profile for each process implant variant with a slightly larger gate-to-gate pitch.

Figure 3: The top diagram shows more space for the contacts with the 140-nm pitch and 3 gate lengths of the TSMC 28HPC process compared to the 28HPM process on the bottom.


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